US4772936A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pretestable double-sided tab design
Assignee: Frontgrade Colorado Springs LLC
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Filing: 1987-04-07
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Granted: 1988-09-20
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Expires: 2007-04-07
Abstract
Abstract In a packaged electronic circuit, the circuit or circuits is soldered to a flexible tape, then tested and, any defective elements replaced. The tape is then soldered to a package. Different tapes may be used to change the pin-out of a chip; or to accomodate two sets of chips having different contact arrays.
Inventors
- 👤 Bennett J. Reding
- 👤 Chandler H. McIver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:13
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/701; H10P; H10P74/00; H10P74/27; H10P74/273; H10W70/00; H10W70/40; H10W70/453; H10W72/071; H10W72/077
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
An electronic system for inserting in a package comprising at least one integrated circuit chip having chip electrical contacts formed, in a first chip surface thereof, a dielectric support member, having a network of conductive lines thereon, at least some of said network of conductive lines in a connector array on a first support side of said dielectric support member being connected to at least some of said chip electrical contacts; characterized in that: said chip electrical contacts are non-compression bonded to said network of conductive lines at locations in said network of conductive lines that are located on said support side and are supported by said dielectric support member, whereby said first chip surface and said first support side face one another so that access to said chip electrical contacts is not possible, which network includes a group of test pad contacts disposed on said support member and being displaced from said integrated circuit chip and a group of input/output contacts, whereby said at least one integrated circuit chip may be tested before said input/output contacts are connected to said package.
Claim 2
Dependent Claim
182 words
An electronic system for inserting in a package comprising at least one integrated circuit chip having chip electrical contacts formed, in a first chip surface thereof, a dielectric support member, having a network of conductive lines thereon, at least some of said network of conductive lines in a connector array on a first support side of said dielectric support member being connected to at least some of said chip electrical contacts; characterized in that: said chip electrical contacts are non-compression bonded to said network of conductive lines at locations in said network of conductive lines that are located on said support side and are supported by said dielectric support member, whereby said first chip surface and said first support side face one another so that access to said chip electrical contacts is not possible, which network includes a group of test pad contacts disposed on said support member and being displaced from said integrated circuit chip and a group of input/output contacts, whereby said at least one integrated circuit chip may be tested before said input/output contacts are connected to said package.
Claim 3
Dependent Claim
51 words
A system according to claim 1, further characterized in that said dielectric support member is a flexible carrier tape; said at least one integrated circuit includes at least one circuit on a first side of said carrier tape and at least one circuit on a second side of said carrier tape.
Claim 4
Dependent Claim
76 words
A system according to claim 1, further characterized in that said input/output contacts are located within a central portion of said network of conductive lines, and test pad contacts extend outwardly from said central portion of said network of conductive lines over an aperture in said carrier tape to a corresponding outer test pad contact, whereby said test pad contacts may be severed from that portion of said electronic system that is inserted in said package.
Claim 5
Dependent Claim
74 words
An electronic system according to claim 1, further characterized in that said network of conductive lines includes a first connector array and a second connector array also on said first support side and overlapping said first connector array, said first and second connector arrays being connected to portions of the same group of input/output contacts, whereby the same dielectric substrate may be used with chips matching either of said first or second connector arrays.
Claim 6
Dependent Claim
22 words
An electronic system according to claim 4, further characterized in that said second connector array is enclosed within said first connector array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |