Integrated circuit chip carrier

Claim 1

A method of forming a pin grid integrated chip carrier comprising from two layers of plastics material the upper with a central chip mounting area and the lower with pins disposed in the desired array comprising: (a) forming an upper sheet by printed circuit techniques comprising a series of carrier arrays each consisting of a central chip mounting area and metallised paths from adjacent to said area to points in zones disposed around each proposed carrier array and inwardly of the proposed edges thereof, (b) forming a second layer of plastics material with a series of arrays of openings each array corresponding to a desired array of pins, (c) the upper surface of the second sheet or the lower surface of the first sheet having second metallised paths formed by printed circuit techniques from points in the zones to locations corresponding to the openings. (d) binding together the two layers, (e) either before or after assembly (i) forming holes in at least the upper layer in the points in the zones. (ii) metallising the holes to provide connections between the metallised paths on the upper surface of the upper layer and the second metallised paths, (iii) optionally metallising the openings, (f) applying to the upper layer a grid of plastics material each arm of the grid lying above and on both sides of a proposed edge between two adjacent carriers, (g) separating the carrier by cutting along the edge lines, (h) either before or after separating insert heads of pins into the openings with means for retaining said heads and providing electrical connectors to the metallised paths between the layer of plastics materials. (i) optionally inserting the chip and providing a coating on the chip in the cavity resulting from the grid arms and, if desired applying a cover over the cavity.

Claim 2

A method of forming a pin grid integrated chip carrier comprising from two layers of plastics material the upper with a central chip mounting area and the lower with pins disposed in the desired array comprising: (a) forming an upper sheet by printed circuit techniques comprising a series of carrier arrays each consisting of a central chip mounting area and metallised paths from adjacent to said area to points in zones disposed around each proposed carrier array and inwardly of the proposed edges thereof, (b) forming a second layer of plastics material with a series of arrays of openings each array corresponding to a desired array of pins, (c) the upper surface of the second sheet or the lower surface of the first sheet having second metallised paths formed by printed circuit techniques from points in the zones to locations corresponding to the openings. (d) binding together the two layers, (e) either before or after assembly (i) forming holes in at least the upper layer in the points in the zones. (ii) metallising the holes to provide connections between the metallised paths on the upper surface of the upper layer and the second metallised paths, (iii) optionally metallising the openings, (f) applying to the upper layer a grid of plastics material each arm of the grid lying above and on both sides of a proposed edge between two adjacent carriers, (g) separating the carrier by cutting along the edge lines, (h) either before or after separating insert heads of pins into the openings with means for retaining said heads and providing electrical connectors to the metallised paths between the layer of plastics materials. (i) optionally inserting the chip and providing a coating on the chip in the cavity resulting from the grid arms and, if desired applying a cover over the cavity.