US5841967A
Expired / Lapsed
US
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Method and apparatus for design verification using emulation and simulation
Assignee: Cadence Design Systems Inc
•
Filing: 1996-10-17
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Granted: 1998-11-24
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Expires: 2016-10-17
Abstract
Abstract A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.
Inventors
- 👤 Stephen P. Sample
- 👤 Mikhail Bershteyn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:13
CPC Classifications
G; G06; G06F; G06F8/00; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 74
Claim 1
Independent Claim
92 words
An apparatus for design verification using emulation and simulation comprising: at least one reconfigurable element for emulating a first portion of a design; at least one microprocessor for simulating a second portion of said design, connected to said reconfigurable element so as to minimize time for transferring data between said first portion of said design and said second portion of said design; and an event detector connected to said at least one microprocessor for detecting a plurality of events during design verification, relieving said at least one microprocessor from performing event detection.
Claim 2
Independent Claim
92 words
An apparatus for design verification using emulation and simulation comprising: at least one reconfigurable element for emulating a first portion of a design; at least one microprocessor for simulating a second portion of said design, connected to said reconfigurable element so as to minimize time for transferring data between said first portion of said design and said second portion of said design; and an event detector connected to said at least one microprocessor for detecting a plurality of events during design verification, relieving said at least one microprocessor from performing event detection.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 further comprising a scheduler for scheduling operations that said at least one microprocessor would ordinarily schedule.
Claim 4
Dependent Claim
10 words
The apparatus of claim 1 further comprising a second microprocessor.
Claim 5
Dependent Claim
28 words
The apparatus of claim 3 further comprising a selector for selecting independent fragments of said second portion of said design for parallel execution by each of said microprocessors.
Claim 6
Dependent Claim
25 words
The apparatus of claim 1 further comprising a selector for selecting independent fragments of said second portion of said design for execution by said microprocessor.
Claim 7
Dependent Claim
18 words
The apparatus of claim 1 wherein said at least one reconfigurable element further comprises a reconfigurable interconnect component.
Claim 8
Dependent Claim
18 words
The apparatus of claim 1 wherein said at least one reconfigurable element further comprises a reconfigurable logic component.
Claim 9
Dependent Claim
31 words
The apparatus of claim 6 wherein said at least one reconfigurable element comprises a plurality of reconfigurable logic components, and said reconfigurable interconnect component interconnects said plurality of reconfigurable logic components.
Claim 10
Dependent Claim
16 words
The apparatus of claim 1 further comprising a memory connected to said at least one microprocessor.
Claim 11
Dependent Claim
17 words
The apparatus of claim 1 further comprising a bus controller connected to said at least one microprocessor.
Claim 12
Dependent Claim
18 words
The apparatus of claim 1 wherein said second portion of said design is described in a behavioral language.
Claim 13
Dependent Claim
11 words
The apparatus of claim 1 further comprising a second reconfigurable element.
Claim 14
Dependent Claim
41 words
The apparatus of claim 12 wherein said second reconfigurable element further comprises a scheduler for scheduling fragments of said second portion of said design to be simulated by said at least one microprocessor upon detection of events by said event detector.
Claim 15
Dependent Claim
33 words
The apparatus of claim 12 wherein said second reconfigurable element further comprises a selector for selecting independent fragments of said second portion of said design for execution by said at least one microprocessor.
Claim 16
Dependent Claim
34 words
The apparatus of claim 12 wherein said second reconfigurable element further comprises a detector for detecting said plurality of events during design verification, relieving said at least one microprocessor from performing said event detection.
Claim 17
Dependent Claim
22 words
The apparatus of claim 12 further comprising an interconnect element connecting said at least one reconfigurable element and said second reconfigurable element.
Claim 18
Dependent Claim
24 words
The apparatus of claim 1 further comprising a reconfigurable interconnect element connecting said at least one reconfigurable element and said at least one microprocessor.
Claim 19
Dependent Claim
19 words
The apparatus of claim 10 further comprising a system controller connected to said bus controller through a system bus.
Claim 20
Dependent Claim
17 words
The apparatus of claim 1 further comprising a global bus connected to said at least one microprocessor.
Claim 21
Dependent Claim
24 words
The apparatus of claim 19 wherein said global bus further comprises a plurality of signals connected in parallel to said at least one microprocessor.
Claim 22
Dependent Claim
21 words
The apparatus of claim 19 wherein said global bus further comprises a second line serially connecting said at least one microprocessor.
Claim 23
Dependent Claim
27 words
The apparatus of claim 19 wherein said global bus connects at least one signal between said at least one reconfigurable element and said at least one microprocessor.
Claim 24
Independent Claim
64 words
An apparatus for emulation and simulation comprising: a plurality of simulation modules, each having a microprocessor for simulating a design; a first reconfigurable element for emulating said design, connected to said simulation modules; said plurality of simulation modules further comprising a second reconfigurable element; and said second reconfigurable element comprising an event detector for detecting events to assist said microprocessors in simulating said design.
Claim 25
Independent Claim
64 words
An apparatus for emulation and simulation comprising: a plurality of simulation modules, each having a microprocessor for simulating a design; a first reconfigurable element for emulating said design, connected to said simulation modules; said plurality of simulation modules further comprising a second reconfigurable element; and said second reconfigurable element comprising an event detector for detecting events to assist said microprocessors in simulating said design.
Claim 26
Dependent Claim
22 words
The apparatus of claim 23 wherein at least one of said simulation modules transmits a data value to said first reconfigurable element.
Claim 27
Dependent Claim
22 words
The apparatus of claim 23 wherein at least one of said simulation modules transmits a data value outside of said simulation module.
Claim 28
Dependent Claim
19 words
The apparatus of claim 23 wherein one of said microprocessors transmits a data value to said second reconfigurable element.
Claim 29
Dependent Claim
23 words
The apparatus of claim 23 wherein said second reconfigurable element comprises a decoder to decode a signal received from one of said microprocessors.
Claim 30
Dependent Claim
28 words
The apparatus of claim 27 wherein said second reconfigurable element further comprises a selector that is enabled when said decoder recognizes said signal from one of said microprocessors.
Claim 31
Dependent Claim
26 words
The apparatus of claim 28 wherein said second reconfigurable element further comprises a register for capturing said signal, wherein said register is enabled by said selector.
Claim 32
Dependent Claim
28 words
The apparatus of claim 23 wherein at least one of said plurality of simulation modules receives a data signal from a second of said plurality of simulation modules.
Claim 33
Dependent Claim
24 words
The apparatus of claim 23 wherein at least one of said plurality of simulation modules receives a data signal from said first reconfigurable element.
Claim 34
Dependent Claim
19 words
The apparatus of claim 23 wherein one of said microprocessors receives a data signal from said second reconfigurable element.
Claim 35
Dependent Claim
36 words
The apparatus of claim 23 wherein said second reconfigurable element further comprises a decoder for recognizing a microprocessor signal indicating one of said microprocessors is ready to capture a data value from said second reconfigurable element.
Claim 36
Dependent Claim
28 words
The apparatus of claim 23 wherein said second reconfigurable element further comprises a multiplexer that selects a data value for capture by one of said plurality of microprocessors.
Claim 37
Dependent Claim
24 words
The apparatus of claim 23 wherein said event detector causes an interrupt to one of said plurality of microprocessors when an event is detected.
Claim 38
Dependent Claim
19 words
The apparatus of claim 23 further comprising a plurality of event detector groups that process a plurality of events.
Claim 39
Dependent Claim
18 words
The apparatus of claim 36 wherein said plurality of event detector groups comprise at least one event detector.
Claim 40
Dependent Claim
19 words
The apparatus of claim 36 wherein said plurality of event detector groups further comprise at least one AND gate.
Claim 41
Dependent Claim
20 words
The apparatus of claim 36 wherein said plurality of event detector groups process a first event before a second event.
Claim 42
Dependent Claim
30 words
The apparatus of claim 36 wherein said plurality of eve nt detectors detect a first event and a second event and process said first event prior to said second event.
Claim 43
Dependent Claim
29 words
The apparatus of claim 40 wherein said plurality of event detectors create a first busy signal representing said first event and a second busy signal representing said second event.
Claim 44
Dependent Claim
36 words
The apparatus of claim 36 wherein said plurality of event detector groups detect a first busy signal and a second busy signal, and process said second busy signal when said first busy signal is not asserted.
Claim 45
Dependent Claim
35 words
The apparatus of claim 42 wherein each of said first busy signal and said second busy signal are individually formed with an OR gate connected to at least one of said plurality of event detectors.
Claim 46
Dependent Claim
36 words
The apparatus of claim 42 wherein each of said firs t busy signal and said second busy signal are individually formed with a wired OR connected to at least one of said plurality of event detectors.
Claim 47
Dependent Claim
15 words
The apparatus of claim 23 wherein a global bus connects said plurality of simulation modules.
Claim 48
Dependent Claim
27 words
The apparatus of claim 42 further comprising a global bus that transmits said first busy signal and said second busy signal to said plurality of simulation modules.
Claim 49
Dependent Claim
17 words
The apparatus of claim 36 wherein said plurality of event detectors detect a plurality of event types.
Claim 50
Dependent Claim
36 words
The apparatus of claim 47 wherein said simulation modules further comprise a simulation advancement circuit that produces a time advance signal when said plurality of event types are not detected by said plurality of event detectors.
Claim 51
Dependent Claim
17 words
The apparatus of claim 48 wherein said simulation advancement circuit comprises a counter and a NOR gate.
Claim 52
Dependent Claim
16 words
The apparatus of claim 48 further comprising a global bus that transmits said time advance signal.
Claim 53
Dependent Claim
17 words
The apparatus of claim 23 wherein said plurality of simulation modules are connected by a multiplexed bus.
Claim 54
Dependent Claim
19 words
The apparatus of claim 51 where in said multiplexed bus transfers said events between said plurality of simulation modules.
Claim 55
Dependent Claim
21 words
The apparatus of claim 51 wherein said plurality of simulation modules further comprise a transmit controller for controlling said multiplexed bus.
Claim 56
Dependent Claim
18 words
The apparatus of claim 50 wherein said global bus transmits said events between said plurality of simulation modules.
Claim 57
Dependent Claim
14 words
The apparatus of claim 23 wherein said first reconfigurable element comprises a first flip/flop.
Claim 58
Dependent Claim
23 words
The apparatus of claim 55 further comprising a second flip/flop placed downstream from said first flip/flop in order to eliminate a hold-time violation.
Claim 59
Dependent Claim
14 words
The apparatus of claim 23 wherein said first reconfigurable element comprises a clock circuit.
Claim 60
Dependent Claim
12 words
The apparatus of claim 57 wherein said clock circuit comprises a flip/flop.
Claim 61
Dependent Claim
16 words
The apparatus of claim 58 wherein said clock circuit is duplicated in said first reconfigurable element.
Claim 62
Independent Claim
81 words
A method for simulating and emulating a design comprising the following steps: importing said design, where a portion of said design is a behavioral design, to create a behavioral database; dividing said behavioral design into a plurality of behavioral fragments; preprocessing said behavioral database to form a preprocessed behavioral database; generating a plurality of executables for a plurality of simulation modules for processing therein; creating a netlist; and processing said netlist to create configuration data for a plurality of reconfigurable elements.
Claim 63
Independent Claim
81 words
A method for simulating and emulating a design comprising the following steps: importing said design, where a portion of said design is a behavioral design, to create a behavioral database; dividing said behavioral design into a plurality of behavioral fragments; preprocessing said behavioral database to form a preprocessed behavioral database; generating a plurality of executables for a plurality of simulation modules for processing therein; creating a netlist; and processing said netlist to create configuration data for a plurality of reconfigurable elements.
Claim 64
Dependent Claim
32 words
The method in claim 60 wherein said preprocessing step further comprises the following steps: partitioning said behavioral database into a plurality of clusters; and transforming said design to eliminate a hold-time violation.
Claim 65
Dependent Claim
30 words
The method of claim 60 wherein said processing step further includes the following steps: partitioning said netlist creating a partitioned netlist; placing said partitioned netlist; and routing said partitioned netlist.
Claim 66
Independent Claim
70 words
A method for combining emulation and simulation comprising the following steps: connecting an emulator and a plurality of microprocessors so as to minimize time for transferring data between said emulator and said microprocessors; emulating a first portion of a design by said emulator; simulating a second portion of said design by said simulator; and detecting a plurality of events by said emulator that would ordinarily be detected by said microprocessors.
Claim 67
Independent Claim
70 words
A method for combining emulation and simulation comprising the following steps: connecting an emulator and a plurality of microprocessors so as to minimize time for transferring data between said emulator and said microprocessors; emulating a first portion of a design by said emulator; simulating a second portion of said design by said simulator; and detecting a plurality of events by said emulator that would ordinarily be detected by said microprocessors.
Claim 68
Dependent Claim
26 words
The method of claim 63 further comprising the step of scheduling a plurality of operations by said emulator that would ordinarily be scheduled by said microprocessors.
Claim 69
Dependent Claim
32 words
The method of claim 63 further comprising: selecting a plurality of independent fragments of said second portion of said design; and executing said plurality of independent fragments in parallel by said microprocessors.
Claim 70
Dependent Claim
26 words
The method of claim 63 wherein said simulating step further comprises the step of simulating said first portion of said design described in a behavioral language.
Claim 71
Dependent Claim
26 words
The method of claim 63 further comprising the step of manipulating said plurality of events by said emulator that would ordinarily be manipulated by said microprocessors.
Claim 72
Dependent Claim
16 words
The method of claim 63 further comprising the step of eliminating a plurality of hold-time violations.
Claim 73
Dependent Claim
20 words
The method of claim 63 wherein said first portion of said design overlaps with said second portion of said design.
Claim 74
Dependent Claim
22 words
The method of claim 63 wherein said first portion of said design is the same as said second portion of said design.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-23 | 2002-05-25 | 2002-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-23 | 2006-05-25 | 2006-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-23 | 2010-05-25 | 2010-11-24 | $7700.00 | Window Closed / Lapsed |