Emulation devices, systems and methods utilizing state machines

Claim 2

An emulation device which enables a functional circuit to support its own emulation, comprising: a serial scan testability interface having at least first and second scan paths, said first scan path being provided for applying digital information to the functional circuit for use in emulation of the functional circuit; and state machine circuitry connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and corresponding to emulation command codes.

Claim 3

The emulation device of claim 1 wherein said serial scan testability interface comprises a JTAG interface.

Claim 4

The emulation device of claim 1 wherein said second scan path includes scan registers for holding respective emulation command codes.

Claim 5

The emulation device of claim 1 wherein said second scan path includes a scan register for holding domain locking signals.

Claim 6

The emulation device of claim 1 further comprising a processor and a logic circuit for connection to the processor, said logic circuit operable to produce a done signal representing that the processor is done executing an instruction, wherein said second scan path includes a scan register for holding a selection signal determining whether the state machine circuitry is to be responsive to the done signal.

Claim 7

The emulation device of claim 1 for use with a test clock and a functional clock for a processor circuit wherein said second scan path includes a scan register and said state machine circuitry includes clock control circuitry coupling the test clock or the functional clock to the processor circuit depending on a signal in the scan register.

Claim 8

The emulation device of claim 1 for use with a test clock and a functional clock for circuitry having domains wherein said second scan path includes a scan register and said state machine circuitry includes clock control circuitry having respective outputs for the domains so that the clock control circuitry independently couples the test clock to one domain and the functional clock to another domain depending on a signal in the scan register.

Claim 9

The emulation device of claim 1 for use with circuitry having domains wherein said second scan path includes scan registers for holding command codes designating a selected domain and first and second command codes for the selected domain, wherein said state machine circuitry includes emulation control code registers for each of the domains, selection circuitry coupling said scan registers to the emulation control code registers, and a state machine connected to operate the selection circuitry.

Claim 10

The emulation device of claim 1 for use with circuitry to be emulated producing a done signal indicative of a predetermined electrical condition of the circuitry, wherein said state machine circuitry has respective inputs for a start signal from the testability interface and for the done signal.

Claim 11

The emulation device of claim 1 wherein said testability interface includes a decoding circuit having an output signaling to said state machine circuitry when a particular scan path is selected.

Claim 12

The emulation device of claim 1 or use with a test clock connected to said testability interface and a functional clock connected to said state machine circuitry and further comprising a handshake synchronizer connected between said testability interface and said state machine circuitry to produce a start signal for said state machine circuitry in response to said testability interface.

Claim 13

The emulation device of claim 1 wherein said first scan path includes a boundary scan path.

Claim 14

The emulation device of claim 1 for use with circuitry including shift register latches wherein said testability interface includes a third scan path interconnecting said shift register latches.

Claim 15

The emulation device of claim 1 for use with circuitry having domains, wherein said testability interface includes additional scan paths for each of the domains and said second scan path includes a serial register for lock signals, the emulation device further comprising switching circuits connecting the additional scan paths in response to the lock signals.

Claim 16

The emulation device of claim 1 wherein said serial scan testability interface includes an instruction register, and scan path selection circuitry responsive to said instruction register.

Claim 17

The emulation device of claim 15 wherein said serial scan testability interface includes a separate state machine connected to control said instruction register and having a sequence of states responsive to an externally supplied digital signal.

Claim 18

An electronic device, comprising: a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation; a serial scan testability interface on-ship having at least first and second scan paths, said first scan path being provided for applying digital information to said integrated circuit for use in emulation of said integrated circuit; and state machine circuitry on-chip connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said integrated circuit.

Claim 19

An electronic device, comprising: a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation; a serial scan testability interface on-ship having at least first and second scan paths, said first scan path being provided for applying digital information to said integrated circuit for use in emulation of said integrated circuit; and state machine circuitry on-chip connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said integrated circuit.

Claim 20

The electronic device of claim 17 wherein said testability interface includes additional scan paths defining domains in the integrated circuit, and said second scan path includes a serial shift register for lock signals, the device further comprising switching circuits connecting the additional scan paths in response to the lock signals.

Claim 21

The electronic device of claim 17 wherein said second scan path includes scan registers for holding respective emulation command codes.

Claim 22

The electronic device of claim 17 wherein said integrated circuit includes a processor and a logic circuit connected to said processor, said logic circuit operable to produce a done signal for said state machine circuitry representing that the processor is done executing an instruction.

Claim 23

The electronic device of claim 17 wherein said testability interface has additional scan paths defining domains in the integrated circuit, said second scan path including scan registers holding command codes designating a selected domain and first and second command codes for controlling the selected domain, wherein said state machine circuitry includes emulation control code registers for each of the domains, selection circuitry coupling said scan registers to the emulation control code registers, and a state machine connected to operate the selection circuitry.

Claim 24

The electronic device of claim 17 further comprising a circuit responsive to said integrated circuit to produce a done signal indicative of a predetermined electrical condition of the integrated circuit, wherein said state machine circuitry has respective inputs for a start signal from the testability interface and for the done signal.

Claim 25

The electronic device of claim 17 wherein said testability interface includes a decoding circuit having an output to signal to said state machine circuitry when a particular scan path is selected.

Claim 26

The electronic device of claim 17 including a test clock connected to said testability interface and a functional clock connected to said state machine circuitry and further comprising a handshake synchronizer connected between said testability interface and said state machine circuitry to produce a start signal for said state machine circuitry in response to said testability interface.

Claim 27

The electronic device of claim 17 wherein said first scan path includes a boundary scan path.

Claim 28

The electronic device of claim 17 further comprising a test clock and a functional clock wherein said second scan path includes a scan register and said state machine circuitry includes clock control circuitry coupling the test clock or the functional clock to the integrated circuit depending on a signal in the scan register.

Claim 29

The electronic device of claim 26 wherein said clock control circuitry has respective outputs for different domains in the integrated circuit so that the clock control circuitry independently couples the test clock to one domain and the functional clock to another domain depending on the signal in the scan register.

Claim 30

An electronic system comprising a printed wiring board with serial-scan interconnected electronic devices, at least one of the electronic devices including a semiconductor chip with an integrated circuit fabricated thereon, said at least one electronic device being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths, said first scan path being provided for applying digital information to said at least one of the electronic devices for use in emulation of said at least one of the electronic devices, and said at least one of the electronic devices including state machine circuitry on-chip which is connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said at least one of the electronic devices.

Claim 31

An electronic system comprising a printed wiring board with serial-scan interconnected electronic devices, at least one of the electronic devices including a semiconductor chip with an integrated circuit fabricated thereon, said at least one electronic device being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths, said first scan path being provided for applying digital information to said at least one of the electronic devices for use in emulation of said at least one of the electronic devices, and said at least one of the electronic devices including state machine circuitry on-chip which is connected to said second scan path, said state machine circuitry having a sequence of states responsive to said second scan path and providing control signals for use in emulation of said at least one of the electronic devices.

Claim 32

The electronic system of claim 28 wherein said integrated circuit includes a processor and a logic circuit connected to said processor, said logic circuit operable to produce a done signal for said state machine circuitry representing that the processor is done executing an instruction.

Claim 33

The electronic device of claim 28 wherein said testability interface has additional scan paths defining domains in a said integrated circuit, said second scan path including scan registers holding command codes designating a selected domain and first and second command codes for controlling the selected domain, wherein said state machine circuitry includes emulation control code registers for each of the domains, selection circuitry coupling said scan registers to the emulation control code registers, and a state machine connected to said selection circuitry.

Claim 34

The electronic system of claim 28 further comprising a test clock and a functional clock wherein said second scan path includes a scan register and said state machine circuitry includes clock control circuitry coupling the test clock or the functional clock to the integrated circuit depending on a signal in the scan register.

Claim 35

The electronic system of claim 31 wherein said clock control circuitry has respective outputs for different domains in the integrated circuit so that the clock control circuitry independently couples the test clock to one domain and the functional clock to another domain depending on the signal in the scan register.

Claim 36

An electronic system comprising a host computer, a serial scan interface associated with said host computer for downloading testability codes and emulation command codes, and an electronic system connected to said serial scan interface and including a printed wiring board with at least one electronic device that includes a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths for receiving said testability codes and emulation command codes respectively, and state machine circuitry on-chip which is connected to said second scan path and which has a sequence of states responsive to said second scan path, wherein said sequence of states provides control signals for use in emulation of said integrated circuit.

Claim 37

An electronic system comprising a host computer, a serial scan interface associated with said host computer for downloading testability codes and emulation command codes, and an electronic system connected to said serial scan interface and including a printed wiring board with at least one electronic device that includes a semiconductor chip with an integrated circuit fabricated thereon, said integrated circuit being provided to support emulation of its own functional operation, a serial scan testability interface on-chip having at least first and second scan paths for receiving said testability codes and emulation command codes respectively, and state machine circuitry on-chip which is connected to said second scan path and which has a sequence of states responsive to said second scan path, wherein said sequence of states provides control signals for use in emulation of said integrated circuit.

Claim 38

The electronic system of claim 33 wherein said second scan path includes scan registers for holding respective emulation command codes.

Claim 39

The electronic system of claim 33 wherein said integrated circuit includes a processor and a logic circuit connected to said processor, said logic circuit operable to produce a done signal for said state machine circuitry representing that the processor is done executing an instruction.

Claim 40

The electronic system of claim 33 further comprising a test clock and a functional clock wherein said second scan path includes a scan register and said state machine circuitry includes clock control circuitry coupling the test clock or the functional clock to the integrated circuit depending on a signal in the scan register.

Claim 41

The electronic system of claim 36 wherein said clock control circuitry has respective outputs for different domains in the processor circuit so that the clock control circuitry independently couples the test clock to one domain and the functional clock to another domain depending on the signal in the scan register.

Claim 42

The electronic device of claim 33 wherein said testability interface has additional scan paths defining domains in the integrated circuit, said second scan path including scan registers holding command codes designating a selected domain and first and second command codes for controlling the selected domain, wherein said state machine circuitry includes emulation control code registers for each of the domains, selection circuitry coupling said scan registers to the emulation control code registers, and a state machine connected to said selection circuitry.

Claim 43

The electronic system of claim 33 wherein said testability interface includes additional scan paths defining domains in the integrated circuit, and said second scan path includes a serial register for lock signals, the device further comprising switching circuits connecting the additional scan paths in response to the lock signals.

Claim 44

The electronic system of claim 39 wherein said domains include a domain including a processor core, a domain including peripheral circuitry, and a domain including analysis circuitry.

Claim 49

An electronic device, comprising: a semiconductor chip having an integrated circuit fabricated thereon; said integrated circuit including functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions; said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control circuitry being embedded within said integrated circuit; and said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture.

Claim 50

An electronic device, comprising: a semiconductor chip having an integrated circuit fabricated thereon; said integrated circuit including functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions; said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control circuitry being embedded within said integrated circuit; and said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture.

Claim 51

The device of claim 43, wherein said circuitry for selectively driving said embedded control interface includes further state machine circuitry responsive to said first-mentioned state machine circuitry and to said serial scan path for providing control signals for use in operating said embedded interface of said test architecture.

Claim 52

The device of claim 43, wherein said state machine circuitry is a TAP controller according to IEEE STD 1149.1.

Claim 53

The device of claim 43, wherein said state architecture is Modular Port Scan Design architecture.

Claim 54

The device of claim 43, wherein said functional circuitry is operable at a first clock rate to perform said normal operating functions, wherein said data selected by said state machine circuitry is scanned through said serial scan path at a second clock rate which differs from said first clock rate, and wherein said auxiliary circuitry is operable to permit scanning data through said serial scan path at said second clock rate while said functional circuitry is concurrently performing normal operating functions at said first clock rate.

Claim 55

The device of claim 43, wherein said functional circuitry is operable at a first clock rate to perform said normal operating functions, wherein said test architecture includes a further serial scan path extending through said functional circuitry for scanning data through said functional circuitry at a second clock rate which differs from said first clock rate, and wherein said adaptor circuitry is operable to permit scanning data through a portion of said functional circuitry at said second clock rate while another portion of said function circuitry is concurrently performing normal operating functions at said first clock rate.

Claim 56

The device of claim 45, wherein said adaptor circuitry includes a plurality of clock control circuits operatively associated with respective portions of said functional circuitry, wherein said further serial scan path includes a plurality of serially connectable scan path sections operatively associated with respective portions of said functional circuitry, and each said clock control circuit being operable independently of the remaining said clock control circuits for supplying a selected one of a first clock signal having said first clock rate for use by the associated portion of said functional circuit and a second clock signal having said second clock rate for use by the associated scan path section.

Claim 57

The device of claim 48, wherein said first-mentioned serial scan path and said further serial scan path have a common, externally accessible scan data input and are selectively enabled in response to operation of said state machine circuitry to receive data at said scan data input.

Claim 58

An electronic system, comprising: a semiconductor chip having an integrated circuit fabricated thereon: said integrated circuit having functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions; said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control interface being embedded within said integrated circuit; said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture; and wherein said electronic system includes a plurality of said semiconductor chips, said externally accessible inputs of said state machine circuitries being connected together to form a common externally accessible input, and said serial scan paths being connected together in series.

Claim 59

An electronic system, comprising: a semiconductor chip having an integrated circuit fabricated thereon: said integrated circuit having functional circuitry for performing normal operating functions of said integrated circuit, said auxiliary circuitry for performing auxiliary functions that provide information regarding the machine state of said functional circuitry, said auxiliary circuitry including state machine circuitry having an input which is accessible externally of said integrated circuit for permitting external control of said auxiliary functions; said auxiliary circuitry further including a test architecture operatively associated with said functional circuitry and capable of executing operations according to a test methodology, said test architecture having a control interface through which said test architecture is controllable, said control interface being embedded within said integrated circuit; said auxiliary circuitry further including adaptor circuitry interfacing between said state machine circuitry and said test architecture, said adaptor circuitry including a serial scan path for receiving data selected by said state machine circuitry, said adaptor circuitry also including circuitry responsive to said state machine circuitry and said data in said serial scan path for selectively operating said embedded control interface of said test architecture; and wherein said electronic system includes a plurality of said semiconductor chips, said externally accessible inputs of said state machine circuitries being connected together to form a common externally accessible input, and said serial scan paths being connected together in series.

Claim 60

The system of claim 51, wherein said test architecture includes a further serial scan path extending through said functional circuitry for scanning data through said functional circuitry, said first-mentioned serial scan path and said further serial scan path having a common, externally accessible scan data input and a common, externally accessible scan data output, each said scan path being selectively enabled in response to operation of the associated state machine circuitry to receive input data at said scan data input and provide output data at said scan data output.

Claim 61

The system of claim 51, wherein one of said integrated circuits includes a digital signal processor (DSP) and another of said integrated circuits in an application specific integrated circuit (ASIC).

Claim 62

The system of claim 51, wherein one of said integrated circuits includes a microprocessor and another of said integrated circuits is an application specific integrated circuit (ASIC).

Claim 63

The system of claim 51, wherein one of said integrated circuits includes a graphics signal processor and another of said integrated circuits is an application specific integrated circuit (ASIC).

Claim 64

The system of claim 51, wherein one of said integrated circuits includes a graphics signal processor and another of said integrated circuits includes a digital signal processor (DSP).

Claim 65

The system of claim 51, wherein one of said integrated circuits includes a graphics signal processor and another of said integrated circuits includes a microprocessor.

Claim 66

The system of claim 51, wherein one of said integrated circuits includes a digital signal processor (DSP) and another of said integrated circuits includes a microprocessor.

Claim 67

The system of claim 51, wherein said semiconductor chips are provided on a printed circuit board.

Claim 68

The system of claim 51, wherein said functional circuitry of one of said integrated circuits differs from said functional circuitry of another of said integrated circuits.

Claim 69

The system of claim 60, wherein each of said integrated circuits has identical state machine circuitry.

Claim 70

The system of claim 51, wherein said adaptor circuitry of one of said integrated circuits differs from said adaptor circuitry of another of said integrated circuits.

Claim 71

The system of claim 62, wherein each of said integrated circuits has identical state machine circuitry.

Claim 72

The system of claim 51, wherein said test architecture of one of said integrated circuits differs from said test architecture of another of said integrated circuits.

Claim 73

The system of claim 64, wherein each of said integrated circuits has identical state machine circuitry.

Claim 76

The method of claim 66, including scanning data through one portion of said integrated circuit at a first clock rate while another portion of said integrated circuit is concurrently performing normal operation functions at a second clock rate which differs from the first clock rate.

Claim 77

The method of claim 66, including supplying one portion of said integrated circuit with a selected one of a first clock signal having a first clock rate for use in performing normal operating functions and a second clock signal having a second clock rate different form said first clock rate for use in scanning data through said one portion, and performing said supplying step independently of any clock signal concurrently applied to any another portion of said integrated circuit.

Claim 78

The method of claim 66, including performing said scanning step while said integrated circuit is concurrently performing normal operating functions.