Common diagnostic bus for computer systems to enable testing concurrently with normal system operation

Claim 2

In a computer system having a central processing unit (CPU), an I/O channel unit with I/O adapters units connected thereto with at least one I/O adapter unit being a system control adapter, said units including internal storage elements connected for operation in a normal mode and connected serially as a shift ring for operation in a diagnostic mode, the improvement comprising: means in said system control adapter for discretely addressing each unit of said computer system, means in said system control adapter for providing a test signal to each unit of said computer system, and means in each unit of said computer system responsive to being addressed and to receiving said test signal for inhibiting normal mode operation and enabling diagnostic mode operation of said internal storage elements in said responsive unit.

Claim 3

The computer system of claim 1 wherein a unit enabled for diagnostic mode operation of said internal storage elements is tested by said system control adapter concurrently with operation of said computer system provided said unit enabled for diagnostic mode operation of said internal storage elements is other than said CPU.

Claim 4

The computer system of claim 1 wherein said system control adapter includes means for providing data and clocking signals to said internal storage elements of a unit enabled for diagnostic mode operation, said clocking signals causing said enabled unit to perform a predetermined operation.

Claim 5

The computer system of claim 3 wherein said system control adapter further includes means for retrieving data from said internal storage elements of a unit enabled for diagnostic mode operation.

Claim 6

The computer system of claim 3 wherein said system control adapter provides clocking signals to said internal storage elements of a unit enabled for diagnostic mode operation to effect one clock cycle of operation.

Claim 7

The computer system of claim 3 wherein said system control adapter provides clocking signals to said internal storage elements of a unit enabled for diagnositic mode operation to effect one shift cycle of operation.

Claim 8

The computer system of claim 3 wherein said system control adapter provides clocking signals to said internal storage elements of a unit enabled for diagnostic mode operation to effect one instruction cycle of operation.

Claim 9

In a computer system having a CPU unit and including an I/O channel unit with I/O adapter units connected thereto with at least one I/O adapter unit being a system control adapter with means for addressing all other units, means within said system control adapter for providing serial data to an addressed unit and means within said system control adapter for providing a pluraity of common diagnostic control signals to an addressed unit, said units having internal serially connected storage elements which can be set to predetermined states by said system control adapter, the improvement comprising: first logic means includes in each of said units responsive to an address signal and one of said control signals from said system control adapter to block data from passing between said addressed unit and all other units except said system control adapter, second logic means in each of said units responsive to other of said control signals for initiating a diagnostic operation in said addressed unit, sensing means for detecting completion of said diagnostic operation, and means within said system control adapter responsive to said sensing means detecting completion of said diagnostic operation for retrieving serial data from said addressed unit after said diagnostic operation has been executed.

Claim 10

In a computer system having a CPU unit and including an I/O channel unit with I/O adapter units connected thereto with at least one I/O adapter unit being a system control adapter with means for addressing all other units, means within said system control adapter for providing serial data to an addressed unit and means within said system control adapter for providing a pluraity of common diagnostic control signals to an addressed unit, said units having internal serially connected storage elements which can be set to predetermined states by said system control adapter, the improvement comprising: first logic means includes in each of said units responsive to an address signal and one of said control signals from said system control adapter to block data from passing between said addressed unit and all other units except said system control adapter, second logic means in each of said units responsive to other of said control signals for initiating a diagnostic operation in said addressed unit, sensing means for detecting completion of said diagnostic operation, and means within said system control adapter responsive to said sensing means detecting completion of said diagnostic operation for retrieving serial data from said addressed unit after said diagnostic operation has been executed.

Claim 11

The computer system of claim 8 further comprising means within said system control adapter for testing said retrieved serial data.

Claim 12

In a computer system including a CPU unit, an I/O channel unit with I/O adapter units connected thereto with at least one I/O adapter unit being a system control adapter, said units including internal storage elements connected for operation in a normal mode and connected serially as a shift ring for operation in a diagnostic mode, said system control adapter including addressing means for selectively providing address signals to each of said units, means for providing a control signal to each of said units, shift clocking means for selectively providing shift clock signals to each of said units, means for providing serial data to each of said units, and means for receiving serial data from each of said units, said computer system further including, a bus connecting said system control adapter to each of said units for transmitting thereto said address signals, said control signal, said shift clock signals, said serial data and for receving therefrom said serial data, data entry control means in each of said units responsive to an address signal and said shift signals for controlling entry of said serial data into said internal storage elements from said system control adapter via said bus, and means in each of said units responsive to said control signal from said system control adapter via said bus for providing diagnostic clock signals to cause the associated unit having serial data entered therein to modify said serial data.

Claim 13

In a computer system including a CPU unit, an I/O channel unit with I/O adapter units connected thereto with at least one I/O adapter unit being a system control adapter, said units including internal storage elements connected for operation in a normal mode and connected serially as a shift ring for operation in a diagnostic mode, said system control adapter including addressing means for selectively providing address signals to each of said units, means for providing a control signal to each of said units, shift clocking means for selectively providing shift clock signals to each of said units, means for providing serial data to each of said units, and means for receiving serial data from each of said units, said computer system further including, a bus connecting said system control adapter to each of said units for transmitting thereto said address signals, said control signal, said shift clock signals, said serial data and for receving therefrom said serial data, data entry control means in each of said units responsive to an address signal and said shift signals for controlling entry of said serial data into said internal storage elements from said system control adapter via said bus, and means in each of said units responsive to said control signal from said system control adapter via said bus for providing diagnostic clock signals to cause the associated unit having serial data entered therein to modify said serial data.

Claim 14

The computer system of claim 10 where said diagnostic clock signals cause said associated unit having serial data entered therein to effect one clock cycle of operation for modification of said serial data.

Claim 15

The computer system of claim 10 where said diagnostic clock signals cause said associated unit having serial data entered therein to effect one shift cycle of operation for modification of said serial data.

Claim 16

The computer system of claim 10 where said diagnostic clock signals cause said associated unit having serial data entered therein to effect one instruction cycle of operation for modification of said serial data.

Claim 17

The computer system of claim 10 further comprising: means responsive to said address signal and said shift clock signals for controlling exiting of modified serial data from a unit having serial data therein modified by said diagnostic clock signals.

Claim 18

The computer system of claim 14 further comprising analyzing means for analyzing said modified serial data.

Claim 19

The computer system of claim 15 wherein said analyzing means is in said system control adapter.

Claim 20

The computer system of claim 16 wherein siad analyzing means in said system control adapter comprises a shift register containing an expected result pattern, means for shifting said shift register in synchronization with said exiting modified serial data, means for serially comparing said expected result pattern shifted from said shift register with said exiting modified serial data, and means for indicating any non comparison between said expected result pattern and said modified serial data.

Claim 21

In a computer system having a plurality of functional units including a central processing unit, an I/O channel unit connected to said central processing unit and I/O adapter units connected to said channel unit with at least one I/O adapter unit being a system control adapter, said system control adapter including means for generating address signals for discretely addressing said functional units, means for generating a control mode signal, means for providing serial data to and for receiving serial data from said functional units, and means for generating timing signals, each functional unit including internal storage elements connected for independently and serial operation the improvement comprising: bus means connecting said system control adapter directly to each of the other units in said computer system, said bus means including address lines for carrying said address signals from said system control adapter to directly address each of said other units, a control line for applying said control mode signal generated by said system control adapter for each of said other units, a data line for transmitting serial data provided by said system control adapter to each of said other units, a data line for transmitting serial data from each of said other units so said system control adapter, and lines for transmitting said timing signals to each of said other units whereby an addressed other unit receiving a control mode signal isolates itself from other units of said computer system other than said system control adapter and becomes conditioned to receive and send serial data from and to system control adapter under control of said timing signals.

Claim 22

In a computer system having a plurality of functional units including a central processing unit, an I/O channel unit connected to said central processing unit and I/O adapter units connected to said channel unit with at least one I/O adapter unit being a system control adapter, said system control adapter including means for generating address signals for discretely addressing said functional units, means for generating a control mode signal, means for providing serial data to and for receiving serial data from said functional units, and means for generating timing signals, each functional unit including internal storage elements connected for independently and serial operation the improvement comprising: bus means connecting said system control adapter directly to each of the other units in said computer system, said bus means including address lines for carrying said address signals from said system control adapter to directly address each of said other units, a control line for applying said control mode signal generated by said system control adapter for each of said other units, a data line for transmitting serial data provided by said system control adapter to each of said other units, a data line for transmitting serial data from each of said other units so said system control adapter, and lines for transmitting said timing signals to each of said other units whereby an addressed other unit receiving a control mode signal isolates itself from other units of said computer system other than said system control adapter and becomes conditioned to receive and send serial data from and to system control adapter under control of said timing signals.

Claim 23

In a computer system having a plurality of functional units including a central processing unit, an I/O channel unit connected to said central processing unit and I/O adapter units connected to said channel unit with at least one I/O adapter unit being a system control adapter unit, said units including internal storage elements connected for normal operation and connected serially as a shift ring, said internal storage elements having clock inputs and data inputs for normal operation and timing inputs and serial data inputs for serial data scan in and scan out, the improvement comprising: means in said system control adapter unit for discretely addressing each functional unit of said computer system, means in said system control adapter for providing clock control signals to each functional unit, a source of clock signals for said internal storage elements, clock control means for each functional unit connected to receive said clock signals from said source of clock signals and said clock control signals from said system control adapter and responsive to said clock control signals to selectively inhibit and allow transmission of said clock signals to said clock inputs of said internal storage elements of an addressed functional unit, means in said system control adapter for selectively providing timing signals to each functional unit, means in each functional unit responsive to the associated functional unit being addressed for applying said timing signals to said timing inputs of said internal storage elements in said associated functional unit, and means in said system control adapter for providing serial data to said serial data inputs of said internal storage elements in each functional unit whereby said serial data is set into the internal storage elements of said addressed functional unit as said timing signals are applied to said timing inputs while said clock signals are inhibited from said clock inputs under control of said clock control means and whereby said serial data set into said internal storage elements is modified as said clock signals are allowed to be transmitted to said clock inputs under control of said clock control means.

Claim 24

In a computer system having a plurality of functional units including a central processing unit, an I/O channel unit connected to said central processing unit and I/O adapter units connected to said channel unit with at least one I/O adapter unit being a system control adapter unit, said units including internal storage elements connected for normal operation and connected serially as a shift ring, said internal storage elements having clock inputs and data inputs for normal operation and timing inputs and serial data inputs for serial data scan in and scan out, the improvement comprising: means in said system control adapter unit for discretely addressing each functional unit of said computer system, means in said system control adapter for providing clock control signals to each functional unit, a source of clock signals for said internal storage elements, clock control means for each functional unit connected to receive said clock signals from said source of clock signals and said clock control signals from said system control adapter and responsive to said clock control signals to selectively inhibit and allow transmission of said clock signals to said clock inputs of said internal storage elements of an addressed functional unit, means in said system control adapter for selectively providing timing signals to each functional unit, means in each functional unit responsive to the associated functional unit being addressed for applying said timing signals to said timing inputs of said internal storage elements in said associated functional unit, and means in said system control adapter for providing serial data to said serial data inputs of said internal storage elements in each functional unit whereby said serial data is set into the internal storage elements of said addressed functional unit as said timing signals are applied to said timing inputs while said clock signals are inhibited from said clock inputs under control of said clock control means and whereby said serial data set into said internal storage elements is modified as said clock signals are allowed to be transmitted to said clock inputs under control of said clock control means.