US5654649A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable application specific integrated circuit employing antifuses and methods therefor
Assignee: QuickLogic Corp
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Filing: 1995-07-12
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Granted: 1997-08-05
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Expires: 2015-07-12
Abstract
Abstract A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.
Inventors
- 👤 Hua-Thye Chua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
80 words
A method of testing the integrity of a wire segment using logic in a macrocell, said wire segment being directly coupled to said logic, said logic having a scan test output lead, comprising: controlling a programming transistor to be conductive and supplying a first signal through said programming transistor and through said wire segment to said logic in said macrocell; and testing for a second signal on said scan test output lead of said logic corresponding with said first signal.
Claim 2
Independent Claim
80 words
A method of testing the integrity of a wire segment using logic in a macrocell, said wire segment being directly coupled to said logic, said logic having a scan test output lead, comprising: controlling a programming transistor to be conductive and supplying a first signal through said programming transistor and through said wire segment to said logic in said macrocell; and testing for a second signal on said scan test output lead of said logic corresponding with said first signal.
Claim 3
Independent Claim
181 words
A method, comprising: (a) programming an antifuse contacting a wire segment by: controlling a programming transistor coupled to said wire segment to be conductive so that a voltage V1 or a voltage V2 is supplied onto said wire segment, said programming transistor being coupled to said wire segment near a first end of said wire segment; and controlling a control electrode of a test transistor to be substantially nonconductive, a first electrode of said test transistor being coupled to said wire segment near a second end of said wire segment, a second electrode of said test transistor being supplied with an intermediate voltage V during said programming of said antifuse, wherein V1<V<V2 and wherein a voltage of magnitude V2 is adequate to program said antifuse; and (b) testing a length of said wire segment between said programming transistor and said test transistor by: controlling said control electrodes of said programming and test transistors so that said programming and test transistors are conductive; and testing a current path through said programming transistor, said length of said wire segment, and said test transistor.
Claim 4
Independent Claim
181 words
A method, comprising: (a) programming an antifuse contacting a wire segment by: controlling a programming transistor coupled to said wire segment to be conductive so that a voltage V1 or a voltage V2 is supplied onto said wire segment, said programming transistor being coupled to said wire segment near a first end of said wire segment; and controlling a control electrode of a test transistor to be substantially nonconductive, a first electrode of said test transistor being coupled to said wire segment near a second end of said wire segment, a second electrode of said test transistor being supplied with an intermediate voltage V during said programming of said antifuse, wherein V1<V<V2 and wherein a voltage of magnitude V2 is adequate to program said antifuse; and (b) testing a length of said wire segment between said programming transistor and said test transistor by: controlling said control electrodes of said programming and test transistors so that said programming and test transistors are conductive; and testing a current path through said programming transistor, said length of said wire segment, and said test transistor.
Claim 5
Dependent Claim
29 words
The method of claim 2, wherein said programming transistor has a gate width GW1 and wherein said test transistor has a gate width GW2, GW1 being greater than GW2.
Claim 6
Dependent Claim
27 words
The method of claim 3, wherein said antifuse contacts said wire segment at a location on said wire segment between said programming transistor and said test transistor.
Claim 7
Dependent Claim
18 words
The method of claim 2, wherein said test transistor has a gate width of 5 microns or less.
Claim 8
Dependent Claim
59 words
The method of claim 2, wherein said wire segment does not extend into a logic module of a macrocell, a second wire segment extending in a dimension substantially perpendicular to a dimension said wire segment extends, said second segment extending into said logic module, said antifuse being disposed in contact with said wire segment and said second wire segment.
References Cited (Backward Citations)
US3699543A
Cited
US3629863A
Cited
US3987287A
Cited
US4146902A
Cited
US4207556A
Cited
US4177475A
Cited
US4455495A
Cited
US4399372A
Cited
US4499557A
Cited
US4442507A
Cited
US4433331A
Cited
US4543594A
Cited
US4494220A
Cited
US4609830A
Cited
US4609998A
Cited
US4651409A
Cited
US4870302A
Cited
US4670749A
Cited
US4609986A
Cited
US4642487A
Cited
US4924287A
Cited
US4691161A
Cited
US4992679A
Cited
US4949084A
Cited
US4749947A
Cited
US4943538A
Cited
US5134457A
Cited
US4823181A
Cited
US4899205A
Cited
US4881114A
Cited
US4769791A
Cited
US5477165A
Cited
US4857774A
Cited
US5172014A
Cited
US4910417A
Cited
US4873459B1
Cited
US5367208A
Cited
US4873459A
Cited
US5083083A
Cited
US4758745B1
Cited
US5208530A
Cited
US5187393A
Cited
US5015885A
Cited
US5341092A
Cited
US4758745A
Cited
US5309091A
Cited
US5223792A
Cited
EP0265554A1
Cited
US4786904A
Cited
US4855619A
Cited
US4963770A
Cited
US4818988A
Cited
US5049969A
Cited
US4970686A
Cited
US5003200A
Cited
EP0365733A1
Cited
US4910418A
Cited
US4945267A
Cited
US5027012A
Cited
US4995004A
Cited
US5008855A
Cited
US4914055A
Cited
US4972105A
Cited
US4996670A
Cited
US5055718A
Cited
US5017813A
Cited
US5198705A
Cited
US5126282A
Cited
US5194759A
Cited
US5073729A
Cited
US5132571A
Cited
US5191241A
Cited
US5367207A
Cited
US5099149A
Cited
US5130777A
Cited
US5220213A
Cited
US5095228A
Cited
US5196724A
Cited
US5302546A
Cited
US5243226A
Cited
US5341030A
Cited
US5200652A
Cited
US5347519A
Cited
US5493526A
Cited
US5237219A
Cited
US5469077A
Cited
US5304871A
Cited
US5294846A
Cited
US5317698A
Cited
US5349248A
Cited
US5316971A
Cited
US5341043A
Cited
US5374844A
Cited
US5371414A
Cited
US5399923A
Cited
US5488317A
Cited
US5504440A
Cited
US5504439A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |