US5317698A
Expired / Lapsed
US
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FPGA architecture including direct logic function circuit to I/O interconnections
Assignee: Microsemi SoC Corp
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Filing: 1992-08-18
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Granted: 1994-05-31
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Expires: 2012-08-18
Abstract
Abstract A user-programmable FPGA architecture includes a plurality of logic function circuits including inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and each include an input buffer having an input connected to I/O pad on the integrated circuit and an output connected to an output node, and an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the input nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the control nodes of selected ones of the I/O modules.
Inventors
- 👤 King W. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/17704
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
371 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of one of said input/output modules.
Claim 2
Dependent Claim
371 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of one of said input/output modules.
Claim 3
Dependent Claim
38 words
The user-programmable FPGA architecture of claim 1 further comprising at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 4
Dependent Claim
39 words
The user-programmable FPGA architecture of claim 1 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 5
Dependent Claim
371 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 6
Dependent Claim
371 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 7
Dependent Claim
39 words
The user-programmable FPGA architecture of claim 4 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 8
Dependent Claim
373 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 9
Dependent Claim
373 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 10
Dependent Claim
437 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of a selected one of said input/output modules; at least one direct interconnect conductor connected between the input of a selected one of said logic function circuits and the output node of said selected one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the control input node of said selected one of said input/output modules.
Claim 11
Dependent Claim
437 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of first interconnect conductors and a plurality of second interconnect conductors superimposed on said array, said first interconnect conductors disposed parallel to one another and running in a first direction, said second interconnect conductors disposed parallel to one another and running in a second direction substantially perpendicular to said first direction, a plurality of interconnect intersections located where individual ones of said first interconnect conductors cross individual ones of said second interconnect conductors, said first interconnect conductors and said second interconnect conductors forming a grid of interconnect conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said first interconnect conductors and selected ones of said second interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of a selected one of said input/output modules; at least one direct interconnect conductor connected between the input of a selected one of said logic function circuits and the output node of said selected one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the control input node of said selected one of said input/output modules.
Claim 12
Dependent Claim
334 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of one of said input/output modules.
Claim 13
Dependent Claim
334 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the input node of one of said input/output modules.
Claim 14
Dependent Claim
38 words
The user-programmable FPGA architecture of claim 8 further comprising at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 15
Dependent Claim
39 words
The user-programmable FPGA architecture of claim 8 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 16
Dependent Claim
334 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 17
Dependent Claim
334 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an input of a selected one of said logic function circuits and an output node of one of said input/output modules.
Claim 18
Dependent Claim
39 words
The user-programmable FPGA architecture of claim 11 further comprising at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 19
Dependent Claim
335 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 20
Dependent Claim
335 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and a control input node of one of said input/output modules.
Claim 21
Dependent Claim
400 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductors; connected between an output of a selected one of said logic function circuits and the input node of a selected one of said input/output modules; at least one direct interconnect conductor connected between the input of a selected one of said logic function circuits and the output node of said selected one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the control input node of said selected one of said input/output modules.
Claim 22
Dependent Claim
400 words
A user-programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: an array including a plurality of logic function circuits, each of said logic function circuits having a plurality of inputs and at least one output; a plurality of input/output pads; a plurality of input/output modules, each input/output module including an input node, an output node, a control node, an input buffer having an input communicating with one of said input/output pads and an output communicating with said output node, and an output buffer having an input communicating with said input node, an output communicating with said one of said input/output pads, and a control input communicating with said control node, said control input for selectively placing said output buffer in a high impedance state; a general interconnect structure including a plurality of interconnect conductors superimposed on said array, said interconnect conductors disposed parallel to one another and running in a direction, a plurality of interconnect intersections located where individual ones of said interconnect conductors cross input conductors and output conductors connected to said logic function circuits, said interconnect conductors, said input conductors, and said output conductors forming a grid of conductors which surrounds a plurality of said logic function circuits; a plurality of user-programmable interconnect elements, first individual ones of said interconnect elements connected between said inputs of said logic function circuits and selected ones of said interconnect conductors, second individual ones of said interconnect elements connected between said outputs of said logic function circuits and selected ones of said interconnect conductors, third individual ones of said interconnect elements connected between selected ones of said interconnect conductors at selected ones of said interconnect intersections, and fourth individual ones of said interconnect elements connected between said input nodes and said output nodes of said input/output modules and selected ones of said interconnect conductors; and at least one direct interconnect conductors; connected between an output of a selected one of said logic function circuits and the input node of a selected one of said input/output modules; at least one direct interconnect conductor connected between the input of a selected one of said logic function circuits and the output node of said selected one of said input/output modules; and at least one direct interconnect conductor connected between an output of a selected one of said logic function circuits and the control input node of said selected one of said input/output modules.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |