US5220215A
Expired / Lapsed
US
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Field programmable logic array with two or planes
Assignee: Micron Technology Inc
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Filing: 1992-05-15
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Granted: 1993-06-15
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Expires: 2012-05-15
Abstract
Abstract A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.
Inventors
- 👤 Kurt P. Douglas
- 👤 Paul S. Zagar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:56
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
113 words
An integrated circuit, comprising: (a) a plurality of circuit input lines; (b) a plurality of logical AND gates (115A-F); (c) a first programmable matrix, coupling said plurality of input lines to the inputs of said plurality of logical AND gates; (d) a first plurality of logical OR gates (118A-C); (e) a second programmable matrix, coupling the outputs of said plurality of logical AND gates to the inputs of said first plurality of logical OR gates; (f) a second plurality of logical OR gates (120A-C) having inputs coupled to the outputs of said plurality of logical AND gates; and (g) a plurality of memory elements exclusively coupled to said first plurality of OR gates.
Claim 2
Dependent Claim
113 words
An integrated circuit, comprising: (a) a plurality of circuit input lines; (b) a plurality of logical AND gates (115A-F); (c) a first programmable matrix, coupling said plurality of input lines to the inputs of said plurality of logical AND gates; (d) a first plurality of logical OR gates (118A-C); (e) a second programmable matrix, coupling the outputs of said plurality of logical AND gates to the inputs of said first plurality of logical OR gates; (f) a second plurality of logical OR gates (120A-C) having inputs coupled to the outputs of said plurality of logical AND gates; and (g) a plurality of memory elements exclusively coupled to said first plurality of OR gates.
Claim 3
Dependent Claim
24 words
An integrated circuit as in claim 1, further comprising: a plurality of output pads (126A-C) having inputs from said first and second OR arrays.
Claim 4
Dependent Claim
109 words
A programmable logic device, comprising: (a) a plurality of circuit input lines; (b) a plurality of logical AND gates; (c) a first matrix array coupling input liens to the inputs of said plurality of logical AND gates; (d) a first plurality of logical OR gates; (e) a second matrix array coupling the outputs of said plurality of logical AND gates to the inputs of said first plurality of logical OR gates; (f) a second plurality of logical OR gates, having inputs coupled to the outputs of said plurality of logical AND gates; and (g) a plurality of memory elements exclusively coupled to said first plurality of logical OR gates.
Claim 5
Dependent Claim
109 words
A programmable logic device, comprising: (a) a plurality of circuit input lines; (b) a plurality of logical AND gates; (c) a first matrix array coupling input liens to the inputs of said plurality of logical AND gates; (d) a first plurality of logical OR gates; (e) a second matrix array coupling the outputs of said plurality of logical AND gates to the inputs of said first plurality of logical OR gates; (f) a second plurality of logical OR gates, having inputs coupled to the outputs of said plurality of logical AND gates; and (g) a plurality of memory elements exclusively coupled to said first plurality of logical OR gates.
Claim 6
Dependent Claim
14 words
A programmable logic device as in claim 3, wherein: said first matrix is programmable.
Claim 7
Dependent Claim
14 words
A programmable logic device as in claim 3, wherein: said second matrix is programmable.
Claim 8
Dependent Claim
82 words
An integrated circuit, comprising: (a) a programmable logic device (PLD) having a plurality of logical AND gates and a first and second plurality of logical OR gates; (b) said PLD having two signal paths for the inputs to the outputs of said PLD, where the first signal path exclusively utilizes the first plurality of logical OR gates and a memory element, and the second signal path exclusively utilizes the second plurality of logical OR gates and does not utilize a memory element.
Claim 9
Dependent Claim
82 words
An integrated circuit, comprising: (a) a programmable logic device (PLD) having a plurality of logical AND gates and a first and second plurality of logical OR gates; (b) said PLD having two signal paths for the inputs to the outputs of said PLD, where the first signal path exclusively utilizes the first plurality of logical OR gates and a memory element, and the second signal path exclusively utilizes the second plurality of logical OR gates and does not utilize a memory element.
Claim 10
Dependent Claim
18 words
An integrated circuit as in claim 6 wherein said first and second signal paths share common output pads.
Claim 11
Dependent Claim
91 words
An integrated circuit, comprising: (a) a programmable logic device (PLD) having a plurality of logical AND gates, a first logical OR gate, a second logical OR gates, a latch receiving signals exclusively from the first OR gate, the OR gates receiving signals form the AND gates; (b) an outputting means for outputting a latched or non-latched signal, wherein said latched signal is exclusively from said latch and said non-latched signal originates exclusively from said second logical OR; and (c) said latched and non-latched signals are outputted over a common output pad.
Claim 12
Dependent Claim
91 words
An integrated circuit, comprising: (a) a programmable logic device (PLD) having a plurality of logical AND gates, a first logical OR gate, a second logical OR gates, a latch receiving signals exclusively from the first OR gate, the OR gates receiving signals form the AND gates; (b) an outputting means for outputting a latched or non-latched signal, wherein said latched signal is exclusively from said latch and said non-latched signal originates exclusively from said second logical OR; and (c) said latched and non-latched signals are outputted over a common output pad.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |