US3566153A
Expired / Lapsed
US
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Programmable sequential logic
Assignee: Texas Instruments Inc
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Filing: 1969-04-30
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Granted: 1971-02-23
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Expires: 1989-04-30
Abstract
Abstract A mass production sequential logic circuit which can be custom programmed by modification of a single fabrication mask to perform sequential combinational logic is disclosed. The circuit includes a first programmable matrix of voltage controlled devices for generating product terms, a second programmable matrix of voltage controlled devices for summing the product terms, a plurality of binary storage elements such as flip-flops or shift registers, input inverters and output buffers on the same semiconductor substrate. The outputs of the second matrix are applied either to the inputs of the storage elements, or to the output buffers, or both. The outputs of the storage elements are applied either to inputs of the first matrix, or to output buffers, or both.
Inventors
- 👤 Ralph F Spencer Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:07
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223; G11C17/10; G11C17/12; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K23/00; H03K23/002; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
64 words
The logic circuit comprising a product term generator, a sum of product term generator, and at least 1 binary storage element formed on a substrate, the outputs of the product term generator being connected to the input of the sum of product term generator, and the input of the binary storage element being connected to an output of the sum of product term generator.
Claim 2
Dependent Claim
64 words
The logic circuit comprising a product term generator, a sum of product term generator, and at least 1 binary storage element formed on a substrate, the outputs of the product term generator being connected to the input of the sum of product term generator, and the input of the binary storage element being connected to an output of the sum of product term generator.
Claim 3
Dependent Claim
133 words
The logic circuit of claim 1 wherein the product term generator and the sum of product term generator each comprises: at least three generally parallel, elongated regions of one conductivity type formed in a substrate of the other conductivity type; a layer of insulation disposEd over the surface of the substrate; and a plurality of generally parallel, conductive strips disposed over the layer of insulation and extending over at least three of said elongated regions at angles thereto to form potential transistors at the intersections of the conductive strips and adjacent pairs of said elongated regions of the other conductivity type; the relationship of the adjacent said elongated regions, the areas of the conductive strips, and the layer of insulation at said intersections being such as to form transistors only at selected intersections.
Claim 4
Dependent Claim
116 words
The logic circuit of claim 1 wherein the product term generator comprises: a plurality of MOS transistors, the transistors being arrayed in a number of input rows and a number of output columns, the input rows and output columns being disposed generally in orthogonal relationship, the gates of the transistors in each input row being common, the drains of the transistors in each output column being common and being connected through a load resistance to the drain supply voltage, and the sources of all of the transistors being common, and the number of actual transistors in at least one output column being less than the number of true inputs to said at least one output column.
Claim 5
Dependent Claim
98 words
The logic circuit of claim 3 wherein the sum of product term generator comprises: a second plurality of MOS transistors, said second plurality of transistors being arrayed in a number of input columns and a number of output rows, the input columns and output rows being disposed generally in orthogonal relationship, the gates of the transistors in each input column being common, the drains of the transistors in each output row being common and being connected through a load resistance to a drain supply voltage, and the sources of all of the second plurality of transistors being common.
Claim 6
Dependent Claim
29 words
The logic circuit defined in claim 4 wherein the output of at least 1 binary storage element is connected to at least one input of the product term generator.
Claim 7
Dependent Claim
20 words
The logic circuit defined in claim 5 wherein the circuit includes a plurality of flip-flops each comprised of MOS transistors.
Claim 8
Dependent Claim
18 words
The logic circuit defined in claim 5 wherein the circuit includes a shift register comprised of MOS transistors.
Claim 9
Dependent Claim
155 words
The logic circuit comprising: a product term generator having a plurality of binary inputs, a plurality of product term outputs, and logic means for producing logic signals on selected product term outputs representative of the complement of the logical products of the logic signals at selected binary inputs; a sum of product term generator having a plurality of product term inputs connected to the product term outputs, a plurality of sum of product term outputs, and logic means for producing a logic signal on selected sum of product term outputs representative of the complement of the sum of selected logic signals at the product term inputs; and a plurality of binary storage elements each having a logic input and a logic output, the logic inputs of the storage elements being connected to selected logic outputs of the generators and the logic outputs of the storage elements being connected to selected logic inputs of the generators.
Claim 10
Dependent Claim
155 words
The logic circuit comprising: a product term generator having a plurality of binary inputs, a plurality of product term outputs, and logic means for producing logic signals on selected product term outputs representative of the complement of the logical products of the logic signals at selected binary inputs; a sum of product term generator having a plurality of product term inputs connected to the product term outputs, a plurality of sum of product term outputs, and logic means for producing a logic signal on selected sum of product term outputs representative of the complement of the sum of selected logic signals at the product term inputs; and a plurality of binary storage elements each having a logic input and a logic output, the logic inputs of the storage elements being connected to selected logic outputs of the generators and the logic outputs of the storage elements being connected to selected logic inputs of the generators.
References Cited (Backward Citations)
US3493932A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |