Cross-field-partitioning in array logic modules

Claim 2

An array digital signal processor having an array of logic elements with a plurality of columnar input lines logically associatable by predetermined electrical connections in array form with a plurality of columnar output lines, said electrical connections each including electrical switching elements, the improvement including in combination: an encoder circuit having a plurality of output connections to predetermined ones of said columnar input lines and having first and second input portions, said encoder circuit supplying output signals at said output connections dependent upon both said input portions, input means for receiving a plurality of binary signals and means for supplying one of said binary signals to said first input portion, and means connecting at least one of said columnar output lines to said second input portion.

Claim 3

The digital signal processor set forth in claim 1 wherein said array of logic elements has first and second array portions, said first array portion being a rectangular array of logic AND circuits with a plurality of row output lines, said logic AND circuits connecting said columnar input lines to said row output lines in a predetermined array logical AND relationship, said second array being a rectangular array of logic OR circuits and having a plurality of row input lines respectively connected to said row output lines for logically OR connecting said row input lines to said columnar output lines in accordance with a predetermined array logical OR relationship, and said plurality of encoder output connections being in accordance with a predetermined ordered combinational relationship of said input portions such that coaction of said encoder circuit and said first array portion combine signals from said input portions in a negative logic manner within said first array portion.

Claim 4

The digital signal processor set forth in claim 1 wherein said connecting means further includes a storage register, and said storage register having input connections to a predetermined ones of said columnar output lines and having an output connection to said second input portion.

Claim 5

The digital signal processor set forth in claim 1 further including a plurality of said encoder circuits having output connections to predetermined ones of said columnar input lines and each said encoder circuit having said first and second input portions respectively connected to said input means and respectively to predetermined ones of said columnar output lines.

Claim 6

The digital signal processor set forth in claim 4 wherein said connection means includes a register having a plurality of storage stages, predetermined ones of said storage stages having respective connections to said encoder circuits and to said columnar output lines, and other ones of said storage stages connected to certain ones of said columnar input lines.

Claim 7

An array digital signal processing circuit having a search arrAy of logic AND elements and a read array of logic OR elements, said search array having a plurality of columnar input lines electrically connected to a plurality of row output lines in a predetermined pattern of electrical connections by said logic AND circuits, said read array having row input lines respectively connected to said row output lines and electrically connected to a plurality of columnar output lines in a predetermined pattern of logic OR circuits, the improvement including in combination: a binary to one-of-N (N is a positive integer) encoder for receiving binary signals and supplying an encoded one-of-N signal, separate output means for each of said one-of-N signals, said output means being respectively connected to predetermined ones of said columnar input lines, input means supplying certain binary signals to said encoder, and feedback means receiving binary signals from predetermined ones of said columnar output lines and supplying at least one binary signal to said encoder whereby signals from said read array are partitioned with said input signals.

Claim 8

An array digital signal processing circuit having a search arrAy of logic AND elements and a read array of logic OR elements, said search array having a plurality of columnar input lines electrically connected to a plurality of row output lines in a predetermined pattern of electrical connections by said logic AND circuits, said read array having row input lines respectively connected to said row output lines and electrically connected to a plurality of columnar output lines in a predetermined pattern of logic OR circuits, the improvement including in combination: a binary to one-of-N (N is a positive integer) encoder for receiving binary signals and supplying an encoded one-of-N signal, separate output means for each of said one-of-N signals, said output means being respectively connected to predetermined ones of said columnar input lines, input means supplying certain binary signals to said encoder, and feedback means receiving binary signals from predetermined ones of said columnar output lines and supplying at least one binary signal to said encoder whereby signals from said read array are partitioned with said input signals.