Functional memory using multi-state associative cells

Claim 2

In a functionl memory in which data in storage cells is interrogated by interrogating signals placed on the bit lines of the cell and responds to the interrogation by placing a match or no match signal on the word line of the cell, the improvement comprising: a. a decoder for decoding at least two binary input signals and their complements to provide a multi-variable interrogating signal on three or more lines; b. a multi-state cell having more than four states in a plurality of two state positions each with a bit line coupled to one of the three or more lines to receive an interrogation signal from the decoder and having a single word line on which each of the positions provides a match or no match signal whereby a particular logic function of two or more variables can be performed on the binary input signals by selection of the data stored in the multi-state cell.

Claim 3

The functional memory of claim 1 wherein said decoder has n inputs and decodes to one of the 2n outputs.

Claim 4

The functional memory of claim 1 wherein each of the positions comprises a bistable circuit.

Claim 5

The functional memory of claim 1 wherein each two positions comprises a quadra state circuit.

Claim 6

The functional memory of claim 1 wherein said decoder is a threshold decoder.

Claim 7

The functional memory of claim 5 wherein each of the inputs of the decoder is given equal weight.

Claim 8

The functional memory of claim 5 wherein at least one of the inputs of the decoder is given a different weighted value.

Claim 9

The functional memory of claim 1 including for each word line a plurality of OR circuit inputs which can be selectively coupled or uncoupled to that word line to perform logic on the output of the storage cells and which are coupled to other OR circuit inputs connected to other word lines in the matrix to form a matrix of programmable OR circuits.

Claim 10

The functional memory of claim 8 including a latch circuit for each of at least some output lines of OR circuits said latch circuit selectively coupled or uncoupled to that output line to form a matrix of programmable latches.

Claim 11

In a functional memory in which data in storage cells arranged in a matrix is interrogated with interrogating signals placed on the bit lines for the cells and responds to the interrogation by placing a match or no match signal on the word lines of the cells, comprising: a. a plurality of decoders each for addressing the bit lines of a different group of cells in the matrix to generate interrogation signals from the input signals with at least one of the decoders in the plurality of decoders for decoding at least two binary input signals and their complements into a binary interrogating signal of three or more digits at the output of said one of the decoders, and b. at least one cell in the matrix which has more than four states arranged in a plurality of two-state positions each with a bit line coupled to the output of said one of the decoders to receive one of the digits of the interrogating signal from said one of said decoders, said cell with more than four states being coupled to a single word line on which either a match or no match signal is provided in response to any combination of digits in the binary interrogation signal of three or more digits whereby a number of particular logic functions of two or more variables can be performed on the two binary input signals by selection of the data stored in the one cell with more than four states.

Claim 12

In a functional memory in which data in storage cells arranged in a matrix is interrogated with interrogating signals placed on the bit lines for the cells and responds to the interrogation by placing a match or no match signal on the word lines of the cells, comprising: a. a plurality of decoders each for addressing the bit lines of a different group of cells in the matrix to generate interrogation signals from the input signals with at least one of the decoders in the plurality of decoders for decoding at least two binary input signals and their complements into a binary interrogating signal of three or more digits at the output of said one of the decoders, and b. at least one cell in the matrix which has more than four states arranged in a plurality of two-state positions each with a bit line coupled to the output of said one of the decoders to receive one of the digits of the interrogating signal from said one of said decoders, said cell with more than four states being coupled to a single word line on which either a match or no match signal is provided in response to any combination of digits in the binary interrogation signal of three or more digits whereby a number of particular logic functions of two or more variables can be performed on the two binary input signals by selection of the data stored in the one cell with more than four states.