Bit partitioned monolithic circuit computer system

Claim 1

A monolithic computer system for processing M bits of data, said system comprising: a. a substrate including a plurality of conductive paths for providing electrical interconnection and a source of power, b. M separate monolithic circuit modules connected to said plurality of conductive paths, each of said M modules constituting interconnected operative duplicate elemental units, each elemental unit including decoder means having input and output terminals, memory means having input and output terminals, quasi-arithmetic means having input and output terminals, and control circuitry interconnected thereto, c. each decoder means associated with one of said M monolithic circuit modules connected at its input terminal to receive only a single one of said M bits of data, and connected at its output terminal to said memory means input terminal, d. each memory means output terminal being connected to its quasi-arithmetic means input terminal, e. a first connection means connecting said quasi-arithmetic means output terminal to said memory means, and each module being responsive for logically combining data stored in its memory means with said data stored in its quasi-arithmetic means for processing successive sets of M bits of data, and f. error correction circuitry means connected to each of said M monolithic circuit modules for providing error detection and correction.