Data processing system having auxiliary register storage

Claim 2

In a datA processing apparatus having storage and working registers, the combination comprising: A. a plurality of pairs of associated first and second storage devices; B. means selectively combining said first storage devices to form said storage and working registers of said data processing apparatus; C. means connected to enable each second storage device to register a signal representation of the information stored in said associated first storage device; and, D. means connected to condition each of said second storage devices for transferring stored signal representations received from said first storage devices serially only through said second storage devices.

Claim 3

In a data processing apparatus wherein information is stored and processed in a plurality of conventional storage and working register means, each of which comprises a plurality of storage elements, said data processing apparatus further including: A. a plurality of bistable storage devices corresponding in number to the number of at least selected ones of said elements comprising such storage register means; B. first means serially interconnecting said storage devices; C. second means interconnecting each storage device with one selected storage element associated therewith; and D. control means coupled to said first and second means for effecting the selected duplication of information representations stored in said selected storage elements into said associated bistable devices and for thereafter transferring information representations received from said storage elements serially only through said storage devices.

Claim 4

In a data processing apparatus wherein information is stored and processed in a plurality of conventional storage and working register means, each of which comprises a plurality of storage elements, said data processing apparatus further including: A. a plurality of bistable storage devices corresponding in number to the number of at least selected ones of said elements comprising such storage register means; B. first means serially interconnecting said storage devices; C. second means interconnecting each storage device with one selected storage element associated therewith; and D. control means coupled to said first and second means for effecting the selected duplication of information representations stored in said selected storage elements into said associated bistable devices and for thereafter transferring information representations received from said storage elements serially only through said storage devices.

Claim 5

second control signals for selectively transferring the contents read out from said first register means into said bistable devices associated therewith, and

Claim 6

second control signals for selectively transferring the contents read out from said first register means into said bistable devices associated therewith, and

Claim 7

a plurality of indicator storage means;

Claim 8

a plurality of indicator storage means;

Claim 9

a plurality of indicator storage means;

Claim 10

a plurality of indicator storage means;

Claim 11

indicator logic gating means connecting the storage elements of said display shift register to individual ones of said indicator storage means;

Claim 12

indicator logic gating means connecting the storage elements of said display shift register to individual ones of said indicator storage means;

Claim 13

In a data processing apparatus, the combination comprising: A. a plurality of conventional register means, each of which comprises a number of storage elements; B. a plurality of bistable storage devices whose number is less than the number of said storage elements constituting said register means; C. first means interconnecting only said storage devices to form a shift register; D. second means interconnecting each storage device with one storage element associated therewith; and E. control means coupled to said second means for duplicating the information representations stored in said storage elements into their associated storage devices for serial transfer of said information representations through said shift register for subsequent storage or analysis.

Claim 14

In a data processing apparatus, the combination comprising: A. a plurality of conventional register means, each of which comprises a number of storage elements; B. a plurality of bistable storage devices whose number is less than the number of said storage elements constituting said register means; C. first means interconnecting only said storage devices to form a shift register; D. second means interconnecting each storage device with one storage element associated therewith; and E. control means coupled to said second means for duplicating the information representations stored in said storage elements into their associated storage devices for serial transfer of said information representations through said shift register for subsequent storage or analysis.

Claim 15

third control signals for conditioning said second logic means and said gating means for transferring said memory contents serially through said bistable devices.

Claim 16

third control signals for conditioning said second logic means and said gating means for transferring said memory contents serially through said bistable devices.

Claim 17

indicator logic gating means interconnecting the storage elements of said display shift register to individual ones of said indicator storage means; and B. said control signal generating means includes means for detecting the completion of the serial transfer of said duplicated information to said display means, and for conditioning at that time said indicator logic gating means to duplicate the contents of said display shift register into said indicator storage means for display by said display means.

Claim 18

indicator logic gating means interconnecting the storage elements of said display shift register to individual ones of said indicator storage means; and B. said control signal generating means includes means for detecting the completion of the serial transfer of said duplicated information to said display means, and for conditioning at that time said indicator logic gating means to duplicate the contents of said display shift register into said indicator storage means for display by said display means.

Claim 19

In a data processing system wherein information is processed and stored in a plurality of conventional storage and working register means, each of which comprises plural storage elements, said system further including: A. a group of bistable storage devices; B. first logic gating means interconnecting each said storage device to be associated with a different one of said storage elements of said register means; C. second logic gating means interconnecting each bistable device to form a group of one or more serial auxiliary shift registers; D. a plurality of control lines connected to said first and second logic means; E. means for applying clocking signals to said storage elements and said storage devices; and F. control-signal generating means for cyclically generating command signals on said control lines in a predetermined sequence, said control signal generating means being operative to generate signals on selected control lines for conditioning said first logic gating means to duplicate in each storage device the information contents of the storage element associated therewith, and for conditioning said second logic means to serially transfer, upon the occurrence of successive clocking signals; said information through at least part of said group of said auxiliary shift registers.

Claim 20

In a data processing system wherein information is processed and stored in a plurality of conventional storage and working register means, each of which comprises plural storage elements, said system further including: A. a group of bistable storage devices; B. first logic gating means interconnecting each said storage device to be associated with a different one of said storage elements of said register means; C. second logic gating means interconnecting each bistable device to form a group of one or more serial auxiliary shift registers; D. a plurality of control lines connected to said first and second logic means; E. means for applying clocking signals to said storage elements and said storage devices; and F. control-signal generating means for cyclically generating command signals on said control lines in a predetermined sequence, said control signal generating means being operative to generate signals on selected control lines for conditioning said first logic gating means to duplicate in each storage device the information contents of the storage element associated therewith, and for conditioning said second logic means to serially transfer, upon the occurrence of successive clocking signals; said information through at least part of said group of said auxiliary shift registers.

Claim 21

first sensing means connected with the output of said auxiliary shift register means and the input of said display shift register; and

Claim 22

first sensing means connected with the output of said auxiliary shift register means and the input of said display shift register; and

Claim 23

second sensing means connected with the input of said auxiliary shift register means and said display shift register; and B. said control signal generator means is operable to generate a signal prior to the serial transfer of information through said auxiliary shift register means for loading said first sensing means with a leading sentry bit and is operable to condition said second sensing means for detecting the arrival of said sentry bit.

Claim 24

second sensing means connected with the input of said auxiliary shift register means and said display shift register; and B. said control signal generator means is operable to generate a signal prior to the serial transfer of information through said auxiliary shift register means for loading said first sensing means with a leading sentry bit and is operable to condition said second sensing means for detecting the arrival of said sentry bit.

Claim 25

The apparatus of claim 4 wherein the number of bistable storage devices interconnected to form said shift register is less than the number of storage elements constituting said storage devices of said register means.

Claim 26

In a data processing system having storage and working register means, the combination comprising: A. a plurality of pairs of first and second associated storage devices; B. first means selectively combining said first storage devices to form at least selected ones of said register means; C. second means connected to enable said second storage devices to register a signal representation of information stored in said first storage device associated therewith; D. auxiliary means for displaying or storing the signal representations transferred thereto, and E. control means for transferring the signal representations stored in said second devices serially through others of said second storage devices to said auxiliary means.

Claim 27

In a data processing system having storage and working register means, the combination comprising: A. a plurality of pairs of first and second associated storage devices; B. first means selectively combining said first storage devices to form at least selected ones of said register means; C. second means connected to enable said second storage devices to register a signal representation of information stored in said first storage device associated therewith; D. auxiliary means for displaying or storing the signal representations transferred thereto, and E. control means for transferring the signal representations stored in said second devices serially through others of said second storage devices to said auxiliary means.

Claim 28

A data processing system wherein information is stored in a plurality of conventional register means, each of which comprises plural storage elements, said data processing apparatus further including: A. a plurality of bistable storage devices, each associated with a different storage element of said register means; B. first logic gating means interconnecting each storage device with said storage element associated therewith; C. second logic gating means serially interconnecting each bistable device to form auxiliary shift register means; D. display means connected in series with said shift register means; and E. control signal generating means for cyclically generating control signals for conditioning said first logic gating means for duplicating the information stored in said elements into said bistable devices associated therewith, and for conditioning said second logic gating means to serially transfer said duplicated information through said plurality of bistable devices of said shift register means to said display means.

Claim 29

A data processing system wherein information is stored in a plurality of conventional register means, each of which comprises plural storage elements, said data processing apparatus further including: A. a plurality of bistable storage devices, each associated with a different storage element of said register means; B. first logic gating means interconnecting each storage device with said storage element associated therewith; C. second logic gating means serially interconnecting each bistable device to form auxiliary shift register means; D. display means connected in series with said shift register means; and E. control signal generating means for cyclically generating control signals for conditioning said first logic gating means for duplicating the information stored in said elements into said bistable devices associated therewith, and for conditioning said second logic gating means to serially transfer said duplicated information through said plurality of bistable devices of said shift register means to said display means.

Claim 30

The apparatus of claim 7 wherein A. said display means includes

Claim 31

The apparatus of claim 7 wherein A. said display means includes

Claim 32

The apparatus of claim 9 wherein the storage elements of said display shift register correspond in number to the number of the bistable devices of said auxiliary shift register means.

Claim 33

The apparatus of claim 9 wherein the number of storage elements of said display shift register is less than the number of the bistable devices of said auxiliary shift register means.

Claim 34

The apparatus of claim 8 wherein said display means further includes manUal switching means connected to selected storage elements of said display shift register means, said switching means being adapted to be manually positioned for selectively loading new information established in accordance with the positioning thereof into the storage elements of said display shift register means.

Claim 35

The apparatus of claim 12 wherein said switching means are independently connected to all of the storage elements of said display shift register.

Claim 36

The apparatus of claim 9 wherein said display shift register consists of a pair of serially connected storage elements.

Claim 37

The apparatus of claim 9 wherein said display means further includes manual switching means individually connected to the storage elements of said display register means, said switching means being adapted to be manually positioned for selectively loading new information established in accordance with the positioning of said switching means into the storage elements of said display shift register means.

Claim 38

In a data processing system wherein information is stored in plural conventional storage and working register means, each of which comprises plural storage elements, said system further including: A. a group of bistable storage devices, each of which is associated with a different one of said storage elements; B. first logic gating means interconnecting each bistable device and the storage element associated therewith; C. second logic gating means interconnecting said bistable devices to form a serial auxiliary shift register; D. a plurality of control lines, each of said control lines connected to the same points within said first and second logic means; E. means for applying clocking signals to said storage elements and said bistable devices; and F. control signal generating means connected to said control lines, said control signal generating means being operative during a cycle to generate a number of command signals on said control lines in a predetermined sequence wherein a first control signal applied to a first one of said lines conditions said first logic means to duplicate in each storage device the information contents of the storage elements associated therewith, and a second control signal on a second one of said lines to condition said second logic means to thereafter serially transfer, upon the occurrence of successive clocking signals, said information through said auxiliary shift register; and said control signal generator being operative during the latter portion of said operative cycle to generate a third signal applied to a third one of said control lines for conditioning said first set of logic gating means for duplicating or restoring the contents of said bistable devices into said storage elements.

Claim 39

In a data processing system wherein information is stored in plural conventional storage and working register means, each of which comprises plural storage elements, said system further including: A. a group of bistable storage devices, each of which is associated with a different one of said storage elements; B. first logic gating means interconnecting each bistable device and the storage element associated therewith; C. second logic gating means interconnecting said bistable devices to form a serial auxiliary shift register; D. a plurality of control lines, each of said control lines connected to the same points within said first and second logic means; E. means for applying clocking signals to said storage elements and said bistable devices; and F. control signal generating means connected to said control lines, said control signal generating means being operative during a cycle to generate a number of command signals on said control lines in a predetermined sequence wherein a first control signal applied to a first one of said lines conditions said first logic means to duplicate in each storage device the information contents of the storage elements associated therewith, and a second control signal on a second one of said lines to condition said second logic means to thereafter serially transfer, upon the occurrence of successive clocking signals, said information through said auxiliary shift register; and said control signal generator being operative during the latter portion of said operative cycle to generate a third signal applied to a third one of said control lines for conditioning said first set of logic gating means for duplicating or restoring the contents of said bistable devices into said storage elements.

Claim 40

The apparatus of claim 16 further including means for selectively connecting said third control line in common to said first set of logic gating means of different ones of said storage elements of said working registers whereby the application of said third signal to said third control line conditions said first set of logic means for selective loading of said storage elements of said working registers with the contents of corresponding bistable devices of said auxiliary shift register.

Claim 41

In a data processing system, the combination comprising: A. a plurality of paired storage devices; B. first means selectively combining a first storage device of each said pair to form the various storage and working registers of said data processing system; C. second means connected to enable a second storage device of each said pair to register a signal representation of the information content stored in the first storage device paired therewith; D. means interconnecting said second storage devices to form a shift register; E. control means for transferring the stored signal representation registered in each said second device serially through other said second devices of said shIft register; and F. memory means having a plurality of locations and being connected with one working register of said system, said one register being connected to enable groups of said stored signal representations to be successively duplicated therein from said second storage devices paired therewith for storage in sequential locations of said memory means during the serial transfer of said stored signal representations through said shift register.

Claim 42

In a data processing system, the combination comprising: A. a plurality of paired storage devices; B. first means selectively combining a first storage device of each said pair to form the various storage and working registers of said data processing system; C. second means connected to enable a second storage device of each said pair to register a signal representation of the information content stored in the first storage device paired therewith; D. means interconnecting said second storage devices to form a shift register; E. control means for transferring the stored signal representation registered in each said second device serially through other said second devices of said shIft register; and F. memory means having a plurality of locations and being connected with one working register of said system, said one register being connected to enable groups of said stored signal representations to be successively duplicated therein from said second storage devices paired therewith for storage in sequential locations of said memory means during the serial transfer of said stored signal representations through said shift register.

Claim 43

A data processing system in which register means store information and said register means comprise a number of storage elements, said data processing system further including; A. a plurality of bistable devices, each associated with at least one of said storage elements; B. first sets of logic gating means interconnecting said bistable devices and said associated storage elements; C. second logic gating means serially interconnecting only said bistable devices to form an auxiliary shift register; D. gating means connected in series with said shift register to form a closed loop path; E. memory means having a plurality of addressable memory locations; F. addressing means connected to said memory means for referencing any one of said addressable memory locations during an operative cycle; G. means connecting the output of said memory means with a first register means of said system; and H. control signal generating means for generating, in a predetermined sequence;

Claim 44

A data processing system in which register means store information and said register means comprise a number of storage elements, said data processing system further including; A. a plurality of bistable devices, each associated with at least one of said storage elements; B. first sets of logic gating means interconnecting said bistable devices and said associated storage elements; C. second logic gating means serially interconnecting only said bistable devices to form an auxiliary shift register; D. gating means connected in series with said shift register to form a closed loop path; E. memory means having a plurality of addressable memory locations; F. addressing means connected to said memory means for referencing any one of said addressable memory locations during an operative cycle; G. means connecting the output of said memory means with a first register means of said system; and H. control signal generating means for generating, in a predetermined sequence;

Claim 45

The apparatus of claim 19 wherein said control signal generating means is further operative to generate signals for conditioning said first sets of logic gating means for interchanging the contents of said bistable elements with the contents of the associated storage elements.

Claim 46

The apparatus of claim 20 wherein said control signal generating means is operative to generate a further signal for conditioning one of said first sets of logic gating means for restoring or duplicating the information representations previously stored in the bistable devices in the storage elements associated therewith.

Claim 47

In a data processing apparatus including storage and working registers, the combination comprising; a plurality of associated like first and second storage devices; means selectively combining said first storage devices to form said storage and working registers; first means connected to enable each said second storage device to duplicate simultaneously, a signal representation of the information state of said associated first storage device; and, second means connected to enable each said first storage device to duplicate therein a signal representation of the information state of said associated second device whereby said states of said storage and working registers are temporarily stored in said second storage devices for subsequent restoring.

Claim 48

In a data processing apparatus including storage and working registers, the combination comprising; a plurality of associated like first and second storage devices; means selectively combining said first storage devices to form said storage and working registers; first means connected to enable each said second storage device to duplicate simultaneously, a signal representation of the information state of said associated first storage device; and, second means connected to enable each said first storage device to duplicate therein a signal representation of the information state of said associated second device whereby said states of said storage and working registers are temporarily stored in said second storage devices for subsequent restoring.

Claim 49

The apparatus of claim 22 further including: gating means serially interconnecting each of said second storage devices to form a shift register; a data source coupled to at least one of said second storage devices for serially transferring information signals thereto; and, control means coupled to said gating means for conditioning said second storage devices to serially transfer information signals through said shift register, said control means further including counting means coupled to said data source and being adapted to terminate the transfer of said information signals upon the transfer of a predetermined number of said signals whereafter said control meaNs is connected to condition said second means for duplicating said information signals of said data source into each of said first storage devices.

Claim 50

In a data processing apparatus wherein information is stored and processed in a plurality of conventional storage and working registers, each of which comprises a plurality of basic storage elements, said data processing apparatus further including: a plurality of auxiliary storage devices corresponding in number to the number of at least selected ones of said basic storage elements comprising said registers; first logic AND gating means connecting each said auxiliary storage elements to duplicate the information state of its associated basic storage element, said AND gate including means for receiving a line SNAPOUT; and, second AND gating means for enabling each said basic element to duplicate the information state of its auxiliary storage device, said second AND gating means including means for receiving a line SNAP-IN wherein the successive application of signal levels to said lines SNAPOUT and SNAP-IN enables said auxiliary and basic elements respectively to store and restore the information states of said basic elements as stored prior to the application of said signal level to said line SNAPOUT.

Claim 51

In a data processing apparatus wherein information is stored and processed in a plurality of conventional storage and working registers, each of which comprises a plurality of basic storage elements, said data processing apparatus further including: a plurality of auxiliary storage devices corresponding in number to the number of at least selected ones of said basic storage elements comprising said registers; first logic AND gating means connecting each said auxiliary storage elements to duplicate the information state of its associated basic storage element, said AND gate including means for receiving a line SNAPOUT; and, second AND gating means for enabling each said basic element to duplicate the information state of its auxiliary storage device, said second AND gating means including means for receiving a line SNAP-IN wherein the successive application of signal levels to said lines SNAPOUT and SNAP-IN enables said auxiliary and basic elements respectively to store and restore the information states of said basic elements as stored prior to the application of said signal level to said line SNAPOUT.

Claim 52

The apparatus of claim 24 wherein said first logic AND gate means and said second logic AND gate means respectively further includes means for receiving lines PDA1 and PDA2 and means for applying clocking signals in a predetermined manner to said lines PDA1 and PDA2 whereby said clocking signals produce the interchange of information states between said basic and auxiliary elements when said signal levels are applied jointly to said lines SNAPOUT and SNAP-IN.

Claim 53

The apparatus of claim 24 wherein said apparatus further includes: third AND gating means serially connecting each of said auxiliary storage elements to form an auxiliary shift register, said gating means including means for receiving a line SHIFT; a memory connected to at least one of said auxiliary storage elements for serially transferring information signals thereto; and, control means connected to said second and third AND gating means for applying signal levels to said lines SHIFT and SNAP-IN respectively so as to condition said third AND gating means to serially transfer said information signals through said auxiliary shift register and after the transfer of a predetermined number of said signals, condition said second AND gating means for enabling said selected basic storage elements to duplicate therein the information states of their associated auxiliary storage devices.

Claim 54

In a data processing system wherein information is stored in a plurality of conventional storage devices and working registers, each of which comprises a number of basic storage elements, said system further including: a group of bistable auxiliary storage devices; a first set of AND logic gating means interconnecting each said auxiliary storage device to be associated with a different one of said basic storage elements of said registers; a second set of AND logic gating means interconnecting each auxiliary storage device to form a serial auxiliary shift register; a plurality of control lines SNAP-IN, SNAP-IN, SNAPOUT, SHIFT being connected to the same points within said first and second logic means and clocking lines PDA1 and PDA2 for applying clocking signals to said basic storage elements and auxiliary storage devices respectively; control signal generating means for generating command signal levels to said control lines in a predetermined sequence, said control signal generating means being operative to generate signal levels on said SNAPOUT and SHIFT control lines for conditioning said first and logic gating means to duplicate simultaneously the information contents of the basic storage elements associated therewith in each of said auxiliary storage deviceS, and for conditioning said second AND logic means to thereafter serially transfer, upon the occurrence of successive clocking signals applied to the line PDA2, said information contents through said auxiliary shift register.

Claim 55

In a data processing system wherein information is stored in a plurality of conventional storage devices and working registers, each of which comprises a number of basic storage elements, said system further including: a group of bistable auxiliary storage devices; a first set of AND logic gating means interconnecting each said auxiliary storage device to be associated with a different one of said basic storage elements of said registers; a second set of AND logic gating means interconnecting each auxiliary storage device to form a serial auxiliary shift register; a plurality of control lines SNAP-IN, SNAP-IN, SNAPOUT, SHIFT being connected to the same points within said first and second logic means and clocking lines PDA1 and PDA2 for applying clocking signals to said basic storage elements and auxiliary storage devices respectively; control signal generating means for generating command signal levels to said control lines in a predetermined sequence, said control signal generating means being operative to generate signal levels on said SNAPOUT and SHIFT control lines for conditioning said first and logic gating means to duplicate simultaneously the information contents of the basic storage elements associated therewith in each of said auxiliary storage deviceS, and for conditioning said second AND logic means to thereafter serially transfer, upon the occurrence of successive clocking signals applied to the line PDA2, said information contents through said auxiliary shift register.

Claim 56

The system according to claim 27 further including auxiliary means connected in series with said auxiliary shift register to form a closed loop path, said auxiliary means including switching means for modifying said information contents as they are shifted through said auxiliary shift register prior to being returned to said basic storage elements.