Structure for an easily testable single chip calculator/controller

Claim 1

A testing structure for a microprocessor comprising: combinational network means, said combinational network means comprising a plurality of logic elements wherein said logic elements are capable of being selectively configured in a plurality of combinations; a plurality of data storage elements for containing data, said data storage elements being connected in parallel with said combinational network means by means of an input bus and an output bus; program storage means, said program storage means containing a plurality of instructions; control means for controlling instruction execution; means for selecting one of said plurality of instructions in response to signals from said control means; means for storing said selected instruction; a first means for decoding a portion of said selected instruction to generate a configuration signal for selectively configuring said logic elements of said combinational network means; a second means for decoding the remainder of said selected instruction to generate a storage element select signal for selectively actuating selected storage elements, said data contents of said selected data storage elements being modified by said selectively configured logic elements of said combinational network means; diagnostic testing means connected to said input bus and said output bus; means for selectively routing data flowing along said input bus and said output bus to and from said diagnostic testing means, for selectively testing the operation of said combinational network means and said plurality of data storage elements, respectively; and data clocking means connected to said combinational network means, said control means, and said first decoding means, for controllably sequencing the operation of said combinational network means, said control means, and said first decoding means.