Logic gates with a programmable number of inputs

Claim 2

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate coprising: (a) signal summation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the logical sum of the data input signals and the logical zero signals and for issuing this sum as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each programmable switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the summation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal, wherein each said programmable switch comprises: (1) a first pass transistor of a channel type having an input terminal, a pass terminal and an output terminal, the transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said summation means; and (2) a second pass transistor that has the same channel type and the same terminals as the first pass transistor, having its input terminal connected to a logical zero signal, receiving the logical complement of said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 3

The gate of claim 1, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 4

The gate of claim 2, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 5

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: (a) signal summation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the logical sum of the data input signals and the logical zero signals and for issuing this sum as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each programmable switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the summation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said summation means; and (2) a second pass transistor of a second channel type that is opposite to the first channel type and that has the same terminals as the first pass transistor, having its input terminal connected to a logical zero signal, receiving said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 6

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: (a) signal summation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the logical sum of the data input signals and the logical zero signals and for issuing this sum as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each programmable switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the summation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said summation means; and (2) a second pass transistor of a second channel type that is opposite to the first channel type and that has the same terminals as the first pass transistor, having its input terminal connected to a logical zero signal, receiving said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 7

The gate of claim 4, further including a plurality of control signal sources, with each control signal source being connected to a signal corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 8

The gate of claim 5, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 9

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: (a) signal summation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the logical sum of the data input signals and the logical zero signals and for issuing this sum as an output signal at the output terminal, said signal summation means further including at least one non-programmable input terminal that accepts an input signal irrespective of the state of control signals received at a plurality of programmable switches; and (b) a plurality of individually programmable switches, each programmable switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the summation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal.

Claim 10

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: (a) signal summation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the logical sum of the data input signals and the logical zero signals and for issuing this sum as an output signal at the output terminal, said signal summation means further including at least one non-programmable input terminal that accepts an input signal irrespective of the state of control signals received at a plurality of programmable switches; and (b) a plurality of individually programmable switches, each programmable switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the summation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal.

Claim 11

The gate of claim 7, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 12

The gate of claim 8, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 13

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical one product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said multiplication means; and (2) a second pass transistor that has the same channel type and the same terminals as the first pass transistors, having its input terminal connected to a logical one signal, receiving the logical complement of said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 14

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical one product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said multiplication means; and (2) a second pass transistor that has the same channel type and the same terminals as the first pass transistors, having its input terminal connected to a logical one signal, receiving the logical complement of said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 15

The gate of claim 10, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 16

The gate of claim 11, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EPROMs, RAMs, ROMs, shift registers and registers.

Claim 17

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said multiplication means; and (2) a second pass transistor of a second channel type that is opposite to the first channel type and that has the same terminals as the first pass transistor, having its input terminal connected to a logical one signal, receiving said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 18

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal, wherein each said programmable switch comprises: (1) a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, said transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said multiplication means; and (2) a second pass transistor of a second channel type that is opposite to the first channel type and that has the same terminals as the first pass transistor, having its input terminal connected to a logical one signal, receiving said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 19

The gate of claim 13, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 20

The gate of claim 14, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 21

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal, said signal multiplication means further including at least one non-programmable input terminal that accepts an input signal irrespective of the state of control signals received at a plurality of programmable switches; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal.

Claim 22

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal multiplication, the gate comprising: (a) signal multiplication means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical one input signal at each input terminal and for forming the logical product of the data input signals and the logical one signals and for issuing this product as an output signal at the output terminal, said signal multiplication means further including at least one non-programmable input terminal that accepts an input signal irrespective of the state of control signals received at a plurality of programmable switches; and (b) a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal connected to one of the input terminals of the multiplication means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical one signal.

Claim 23

The gate of claim 16, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 24

The gate of claim 17, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 25

A programmable logic device comprising: EXCLUSIVE-OR logic means having at least one logic gate for forming the EXCLUSIVE-OR function of a set of signals; and means for programming the logic gate for accepting all or a selected subset of input signals, the EXCLUSIVE-OR logic means having input line means for receiving the input signals.

Claim 26

A programmable logic device comprising: EXCLUSIVE-OR logic means having at least one logic gate for forming the EXCLUSIVE-OR function of a set of signals; and means for programming the logic gate for accepting all or a selected subset of input signals, the EXCLUSIVE-OR logic means having input line means for receiving the input signals.

Claim 27

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: EXCLUSIVE-OR signal formation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the EXCLUSIVE-OR signal from the input signals and for issuing this EXCLUSIVE-OR signal as an output signal at the output terminal; and a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the EXCLUSIVE-OR signal formation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal.

Claim 28

A programmable logic gate that may be programmed to accept all or a selected subset of input signals for signal summation, the gate comprising: EXCLUSIVE-OR signal formation means having a plurality of input terminals and an output terminal, for receiving a data input signal or a logical zero input signal at each input terminal and for forming the EXCLUSIVE-OR signal from the input signals and for issuing this EXCLUSIVE-OR signal as an output signal at the output terminal; and a plurality of individually programmable switches, each switch having a data input terminal, a control input terminal and an output terminal, with each output terminal being connected to one of the input terminals of the EXCLUSIVE-OR signal formation means, each data input terminal receiving a data input signal, and each control input terminal receiving a control signal that has a first state and a second state, where receipt of a control signal in the first state causes the output terminal of that switch to issue the data input signal and receipt of a control signal in the second state causes the output terminal of that switch to issue a logical zero signal.

Claim 29

The gate of claim 20, wherein said programmable switch comprises: a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, the transistor receiving said data input signal at its input terminal, receiving said control signal at its pass terminal, and having its output terminal connected to one of said input terminals of said summation means; and a second pass transistor that has the same channel type and terminals as the first pass transistor, having its input terminal connected to a logical zero signal, receiving the logical complement of said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 30

The gate of claim 20, wherein said programmable switch comprises: a first pass transistor of a first channel type having an input terminal, a pass terminal and an output terminal, the transistor receiving said data input signal at its input terminal, receiving said control terminal at its pass terminal, and having its output terminal connected to one of said input terminals of said summation means; and a second pass transistor of a second channel type that is opposite to the first channel type and that has the same terminals as the first pass transistor, having its input terminal connected to a logical zero signal, receiving said control signal at its pass terminal, and having its output terminal connected to the output terminal of the first pass transistor.

Claim 31

The gate of claim 20, wherein said EXCLUSIVE-OR signal formation means further includes at least one non-programmable input terminal that accepts an input signal irrespective of the state of said control signals received at said plurality of programmable switches.

Claim 32

The gate of claim 20, further including a plurality of control signal sources, with each control signal source being connected to a single corresponding control input terminal of said programmable switches, to supply said control signal for said programmable switch.

Claim 33

The gate of claim 24, wherein said control signal source is drawn from a class of sources having two signal values and consisting of fuses, anti-fuses, EPROMs, EEPROMs, RAMs, ROMs, shift registers and registers.

Claim 34

A programmable logic array comprising: a first programmable AND gate having m input terminals to receive m input signals Ai numbered i=1, 2, . . . , m thereat, having m control input terminals to receive m control input signals Ci numbered i=1, 2, . . . m where m is a positive integer, and having an output terminal that issues a logical product output signal 01=(C1·A1+C1*)·(C2·A2+C2*) . . . (Cm·Am+Cm*), wherein at least two of said input signals Ai are the same; a second programmable AND gate having n input terminals to receive n input signals Bj numbered j=1, 2, . . ., n thereat, having n control input terminals to receive n control input signals Dj numbered j=1, 2, . . . , n, where n is a positive integer, and having an output terminal that issues a logical product output signal 02=(D1·B1+D1*)·(D2·B2+D2*) . . . (Dn·Bn+Dn*); and a programmable OR gate having at least first and second input terminals to receive the signals 01 and 02, having at least two control input terminals to receive control input signals E1 and E2, and having an output terminal that issues a logical sum output signal 03=E1·01+E2·02.

Claim 35

A programmable logic array comprising: a first programmable AND gate having m input terminals to receive m input signals Ai numbered i=1, 2, . . . , m thereat, having m control input terminals to receive m control input signals Ci numbered i=1, 2, . . . m where m is a positive integer, and having an output terminal that issues a logical product output signal 01=(C1·A1+C1*)·(C2·A2+C2*) . . . (Cm·Am+Cm*), wherein at least two of said input signals Ai are the same; a second programmable AND gate having n input terminals to receive n input signals Bj numbered j=1, 2, . . ., n thereat, having n control input terminals to receive n control input signals Dj numbered j=1, 2, . . . , n, where n is a positive integer, and having an output terminal that issues a logical product output signal 02=(D1·B1+D1*)·(D2·B2+D2*) . . . (Dn·Bn+Dn*); and a programmable OR gate having at least first and second input terminals to receive the signals 01 and 02, having at least two control input terminals to receive control input signals E1 and E2, and having an output terminal that issues a logical sum output signal 03=E1·01+E2·02.

Claim 36

A programmable logic array comprising: a first programmable AND gate having m input terminals to receive m input signals Ai numbered i=1, 2, . . . , m thereat, having m control input terminals to receive m control input signals Ci numbered i=1, 2, . . . m where m is a positive integer, and having an output terminal that issues a logical product output signal 01=(C1·A1+C1*)·(C2·A2+C2*) . . . (Cm·Am+Cm*), wherein at least two of said input signals Ai are the same; a second programmable AND gate having n input terminals to receive n input signals Bj numbered j=1, 2, . . ., n thereat, having n control input terminals to receive n control input signals Dj numbered j=1, 2, . . . , n, where n is a positive integer, and having an output terminal that issues a logical product output signal 02=(D1·B1+D1*)·(D2·B2+D2*) . . . (Dn·Bn+Dn*); and an OR gate having at least first and second input terminals to receive the signals 01 and 02, and having an output terminal that issues a logical sum output signal 03=01+02.

Claim 37

A programmable logic array comprising: a first programmable AND gate having m input terminals to receive m input signals Ai numbered i=1, 2, . . . , m thereat, having m control input terminals to receive m control input signals Ci numbered i=1, 2, . . . m where m is a positive integer, and having an output terminal that issues a logical product output signal 01=(C1·A1+C1*)·(C2·A2+C2*) . . . (Cm·Am+Cm*), wherein at least two of said input signals Ai are the same; a second programmable AND gate having n input terminals to receive n input signals Bj numbered j=1, 2, . . ., n thereat, having n control input terminals to receive n control input signals Dj numbered j=1, 2, . . . , n, where n is a positive integer, and having an output terminal that issues a logical product output signal 02=(D1·B1+D1*)·(D2·B2+D2*) . . . (Dn·Bn+Dn*); and an OR gate having at least first and second input terminals to receive the signals 01 and 02, and having an output terminal that issues a logical sum output signal 03=01+02.