Inverters and logic gates employing inverters

Claim 2

A circuit element having an input, an output, programmable means including a fusible link and providing either a non-inverting signal path between the said input and output or an inverting signal path between said input and said output, one of said signal paths being operative when said link is intact and the other being operative when said link is fused, and programming means responsive to a programming signal to cause fusing of said link.

Claim 3

A circuit element according to claim 1, wherein said programming means includes a diode in series with said fusible link, to allow passage of a fusing current through said link on application of a programming signal thereto.

Claim 4

A circuit element according to claim 2, comprising an EXCLUSIVE-OR gate, the output of which comprises the output of the circuit element, having a first input directly connected to the input of the circuit element and a second input connected to the input of the circuit element by said diode, the second input of the EXCLUSIVE-OR gate also being connected by a resistor to means for applying a first reference voltage and by a fusible link to means for applying a second reference voltage.

Claim 5

A circuit element according to claim 2, comprising an EXCLUSIVE-OR gate, the output of which comprises the output of the circuit element, having a first input directly connected to the input of the circuit element and a second input connected to the output of the circuit element by said diode, the second input of the EXCLUSIVE-OR gate also being connected by a resistor to means for applying a first reference voltage and by a fusible link to means for applying a second reference voltage.

Claim 6

A circuit element according to claim 2, wherein each of said two signal paths includes a respective fusible link in series therewith, the fusible link being directly connected to the output of the circuit element which is also connected to the diode of the programming means.

Claim 7

An AND gate having a plurality of inputs, each input comprising a respective input circuit adapted to produce a first output of the same polarity as its input at a first output terminal and a second output of opposite polarity to its input at a second output terminal, the first and second output terminals of each input circuit being connected by a first and second fusible link, respectively, to a common circuit point, a resistor connecting said common circuit point to a reference voltage and a diode connecting said common circuit point to an input terminal for recieving a programming signal whereby one or the other of said fusible links is fused depending on the input signal at such input when the programming signal is applied.

Claim 8

An AND gate having a plurality of inputs, each input comprising a respective input circuit adapted to produce a first output of the same polarity as its input at a first output terminal and a second output of opposite polarity to its input at a second output terminal, the first and second output terminals of each input circuit being connected by a first and second fusible link, respectively, to a common circuit point, a resistor connecting said common circuit point to a reference voltage and a diode connecting said common circuit point to an input terminal for recieving a programming signal whereby one or the other of said fusible links is fused depending on the input signal at such input when the programming signal is applied.

Claim 9

A logic gate having at least one input port and at least one output port, at least one of said ports incorporating a circuit element having an input, an output, programmable means including a fusible link and providing either a non-inverting signal path between the said input and output or an inverting signal path between said input and said output, one of said signal paths being operative when said link is intact and the other being operative when said link is fused, and programming means responsive to a programming signal to cause fusing of said link.

Claim 10

A logic gate having at least one input port and at least one output port, at least one of said ports incorporating a circuit element having an input, an output, programmable means including a fusible link and providing either a non-inverting signal path between the said input and output or an inverting signal path between said input and said output, one of said signal paths being operative when said link is intact and the other being operative when said link is fused, and programming means responsive to a programming signal to cause fusing of said link.

Claim 11

A logic gate according to claim 7, comprising an AND gate.

Claim 12

A logic gate according to claim 7, comprising an EXCLUSIVE-OR gate.

Claim 13

A mounting arrangement for an integrated circuit package comprising a socket having a connector for each electrical connection of the integrated circuit, at least one of said connectors comprising a circuit element having an input, an output, programmable means including a fusible link and providing either a non-inverting signal path between the said input and output or an inverting signal path between said input and said output, one of said signal paths being operative when said link is intact and the other being operative when said link is fused, and programming means responsive to a programming signal to cause fusing of said link.

Claim 14

A mounting arrangement for an integrated circuit package comprising a socket having a connector for each electrical connection of the integrated circuit, at least one of said connectors comprising a circuit element having an input, an output, programmable means including a fusible link and providing either a non-inverting signal path between the said input and output or an inverting signal path between said input and said output, one of said signal paths being operative when said link is intact and the other being operative when said link is fused, and programming means responsive to a programming signal to cause fusing of said link.