Morphic exclusive-or circuits

Claim 2

A morphic self-testing Exclusive-OR circuit having as inputs two morphic variable pairs and having as an output a single morphic variable pair, said circuit including means for producing a first output code condition when one and only one input morphic variable pair is in said first code condition and the other input morphic variable pair is in a second code condition and means for producing a second output code condition when both morphic variable input pairs are in said first code condition or both are in said second code condition wherein said first and second code conditions are selectivEly chosen from a first state wherein a given morphic variable pair comprises a 01 or a 10 binary signal and a second state wherein a morphic variable pair comprises a 00 or a 11 binary signal, wherein if one state represents said first code condition, the other state represents the second code condition.

Claim 3

A morphic Exclusive-OR circuit as set forth in claim 1 wherein said morphic Exclusive-OR circuit comprises two, two input single output binary Exclusive-OR circuits, means for connecting one input from each input morphic variable pair to the two inputs of the first binary Exclusive-OR circuit and at least one input not previously used from one of said morphic variable pairs to one input of the second binary Exclusive-OR circuit and wherein the output of at least the second binary Exclusive-OR circuit forms one member of the output morphic variable pair.

Claim 4

A morphic Exclusive-OR circuit as set forth in claim 2 including means for connecting the other said second Exclusive-OR circuit inputs from each of said morphic variable pairs to said second Exclusive-OR circuit and means for taking the outputs from said two binary Exclusive-OR circuits to provide the output morphic variable pair for said morphic Exclusive-OR.

Claim 5

A morphic Exclusive-OR circuit as set forth in claim 3 wherein each binary Exclusive-OR comprises two, two input AND circuits, each AND circuit having as its input the true and inverted signal appearing on the two input lines to said binary Exclusive-OR circuit and the other AND circuit having as its inputs the inverted and the true input signals appearing on the two input lines to said binary Exclusive-OR circuit, the outputs of said two AND circuits being fed to a binary OR circuit, the output of said OR circuit comprising the single line output of said binary Exclusive-OR.

Claim 6

A morphic Exclusive-OR circuit as set forth in claim 2 including means for connecting to said second binary EXclusive-OR circuit the output of said first binary Exclusive-OR and the other input of a first of said morphic variable input pairs, and means for connecting the other input of said second morphic variable input pair directly to the output line of said morphic Exclusive-OR circuit and for connecting the single output from said second binary Exclusive-OR circuit to the other output line of said morphic Exclusive-OR circuit.

Claim 7

A morphic Exclusive-OR circuit as set forth in claim 5 wherein each binary Exclusive-OR comprises two, two input AND circuits, each AND circuit having as its input the true and inverted signal appearing on the two input lines to said binary Exclusive-OR circuit and the other AND circuit having as its input the inverted and the true input signals appearing on the two input lines to said binary Exclusive-OR circuit, the outputs of said two AND circuits being fed to a binary OR circuit, the output of said OR circuit comprising the single line output of said binary Exclusive-OR.

Claim 8

A morphic Exclusive-OR system for performing a morphic Exclusive-OR function on M morphic variable input pairs, said circuit being comprised of M-1 individual two input morphic Exclusive-OR blocks, said blocks being connected to said M morphic variable input pairs so that two morphic variable input pairs are connected to each block and a single morphic variable output pair is produced by each said block, said blocks being connected in a tree circuit configuration to produce a single morphic variable output pair from said M morphic variable input pairs and wherein each individual block comprises an individual morphic Exclusive-OR circuit including means for producing a first output code condition when one and only one input morphic variable pair is in said first code condition and the other input morphic variable pair is in a second code condition and means for producing a second output code condition when both morphic variable input pairs are in said first code condition or both are in said second code condition wherein said first and second code conditions are selectively chosen from a first state wherein a given morphic variable pair comprise a 01 or a 10 binary signal and a second state wherein a morphic variable pair comprises a 00 or a 11 binary signal, wherein if one state represents said first code condition, the other state represents the second code condition.

Claim 9

A morphic Exclusive-OR system for performing a morphic Exclusive-OR function on M morphic variable input pairs, said circuit being comprised of M-1 individual two input morphic Exclusive-OR blocks, said blocks being connected to said M morphic variable input pairs so that two morphic variable input pairs are connected to each block and a single morphic variable output pair is produced by each said block, said blocks being connected in a tree circuit configuration to produce a single morphic variable output pair from said M morphic variable input pairs and wherein each individual block comprises an individual morphic Exclusive-OR circuit including means for producing a first output code condition when one and only one input morphic variable pair is in said first code condition and the other input morphic variable pair is in a second code condition and means for producing a second output code condition when both morphic variable input pairs are in said first code condition or both are in said second code condition wherein said first and second code conditions are selectively chosen from a first state wherein a given morphic variable pair comprise a 01 or a 10 binary signal and a second state wherein a morphic variable pair comprises a 00 or a 11 binary signal, wherein if one state represents said first code condition, the other state represents the second code condition.