Programmable logic device with programmable signal inhibition and inversion means

Claim 2

A programmable logic circuit comprising: a first programmable means for selectively controlling the inhibition and inversion of logic signals applied to various input circuits, logic circuit means coupled to said first programmable means for receiving said controlled signals from said first programmable means, wherein said logic circuit means provides an output signal having a preset relationship with respect to said controlled signals received from said first programmable means, and a second programmable means for receiving said output signal of said logic circuit for selectively inverting said output signal of said logic circuit means.

Claim 3

A programmable logic circuit comprising: a first programmable means for selectively controlling the inhibition and inversion of logic signals applied to various input circuits, logic circuit means coupled to said first programmable means for receiving said controlled signals from said first programmable means, wherein said logic circuit means provides an output signal having a preset relationship with respect to said controlled signals received from said first programmable means, wherein said first programmable means includes multiple exclusive OR gates, each gate having a first input programmably coupled to a voltage potential via a programmable element, a second input for receiving said logic signals, and an output coupled to said logic circuit means, wherein said logic signal which is transmitted to a respective second input of an exclusive OR gate will be inverted at said gate output if said corresponding programmable element of said gate is nonconductive, and wherein said first programmable means further includes multiple OR logic gates, each OR gate having a first input programmably coupled to a voltage potential via a programmable element and a second input coupled to said output of one of said exclusive OR logic gates, wherein an output of said OR gates is coupled to said logic means, said logic signal being inhibited at an output of said OR gate if said corresponding programmable element of said respective OR gate is nonconductive.

Claim 4

A programmable logic circuit comprising: a first programmable means for selectively controlling the inhibition and inversion of logic signals applied to various input circuits, logic circuit means coupled to said first programmable means for receiving said controlled signals from said first programmable means, wherein said logic circuit means provides an output signal having a preset relationship with respect to said controlled signals received from said first programmable means, wherein said first programmable means includes multiple exclusive OR gates, each gate having a first input programmably coupled to a voltage potential via a programmable element, a second input for receiving said logic signals, and an output coupled to said logic circuit means, wherein said logic signal which is transmitted to a respective second input of an exclusive OR gate will be inverted at said gate output if said corresponding programmable element of said gate is nonconductive, and wherein said first programmable means further includes multiple OR logic gates, each OR gate having a first input programmably coupled to a voltage potential via a programmable element and a second input coupled to said output of one of said exclusive OR logic gates, wherein an output of said OR gates is coupled to said logic means, said logic signal being inhibited at an output of said OR gate if said corresponding programmable element of said respective OR gate is nonconductive.

Claim 5

The logic circuit of claim 2, wherein said logic circuit means includes an AND gate having multiple inputs and an output, said inputs of said AND gate are connected to respective outputs of said OR gates.

Claim 6

The logic circuit of claim 3, further including a second programmable means comprising an exclusive OR gate having a first input programmably coupled to a voltage potential via a programmable element and a second input coupled to said output of said logic circuit means, wherein said logic signal is provided to said OR gate from said logic circuit means and is selectively inverted if said programmable element of said exclusive OR gate is nonconductive.

Claim 7

An integrated circuit including: programmable means having a plurality of inputs and an output, said inputs receive data signals , wherein said programmable means further includes a selection means for selectively transmitting said data signals in inverted form, said programmable means further including a means for selectively inhibiting said inputs received from said selection means, wherein said programmable means implements selected logic functions on said received data signals and provides a logic signal at said output, wherein said selection and inhibiting means include programmable element means for selectively inverting and inhibiting, respectively, said data signals which are not selectively inhibited pass through said selection means and inhibiting means without traversing said programmable element means.

Claim 8

An integrated circuit including: programmable means having a plurality of inputs and an output, said inputs receive data signals , wherein said programmable means further includes a selection means for selectively transmitting said data signals in inverted form, said programmable means further including a means for selectively inhibiting said inputs received from said selection means, wherein said programmable means implements selected logic functions on said received data signals and provides a logic signal at said output, wherein said selection and inhibiting means include programmable element means for selectively inverting and inhibiting, respectively, said data signals which are not selectively inhibited pass through said selection means and inhibiting means without traversing said programmable element means.

Claim 9

The integrated circuit of claim 5, wherein said selection means includes a plurality of exclusive OR gates, each having a first input programmably coupled to a voltage potential, a second input coupled to an input of said programmable means, and an output coupled to said inhibiting means.

Claim 10

The integrated circuit of claim 6, wherein said inhibiting means includes a plurality of OR gates, each having a first input programmably coupled to a voltage potential, a second input coupled to said output of said exclusive OR gates and an output.

Claim 11

The integrated circuit of claim 7, wherein said programmable means further includes an AND gate having multiple inputs and an output, said inputs being coupled to respective outputs of said OR gates.

Claim 12

A programmable logic circuit having a plurality of circuit inputs for receiving data signals and a circuit output, said programmable logic circuit comprising: programmable input means having a plurality of inputs coupled to said plurality of circuit inputs and a plurality of outputs, wherein said programmable input means provides for selectively inhibiting said inputs and selectively changing the state of each output, and logic means having a plurality of inputs coupled to said plurality of outputs of said programmable input means and an output coupled to said circuit output for providing an output logic signal at said circuit output according to a predetermined logic relationship between said data signals received from said programmable input means.

Claim 13

A programmable logic circuit having a plurality of circuit inputs for receiving data signals and a circuit output, said programmable logic circuit comprising: programmable input means having a plurality of inputs coupled to said plurality of circuit inputs and a plurality of outputs, wherein said programmable input means provides for selectively inhibiting said inputs and selectively changing the state of each output, and logic means having a plurality of inputs coupled to said plurality of outputs of said programmable input means and an output coupled to said circuit output for providing an output logic signal at said circuit output according to a predetermined logic relationship between said data signals received from said programmable input means.

Claim 14

A programmable logic circuit having a plurality of input lines for receiving data signals and an output line, said programmable logic circuit comprising: programmable input means having a plurality of inputs and a plurality of outputs, said inputs being coupled to said plurality of input lines for receiving said data signals from said input lines, said programmable input means including means for selectively inverting said data signals, and means for selectively inhibiting said data signals; logic means having a plurality of inputs coupled to said outputs of said programmable input means for receiving said data signals and an output coupled to said output line for providing an output logic signal on said output line according to a relationship with said data signals received from said programmable input means, and programmable output means coupled between said output of said logic circuit means and said output line for selectively inverting said output logic signal.

Claim 15

A programmable logic circuit having a plurality of input lines for receiving data signals and an output line, said programmable logic circuit comprising: programmable input means having a plurality of inputs and a plurality of outputs, said inputs being coupled to said plurality of input lines for receiving said data signals from said input lines, said programmable input means including means for selectively inverting said data signals, and means for selectively inhibiting said data signals; logic means having a plurality of inputs coupled to said outputs of said programmable input means for receiving said data signals and an output coupled to said output line for providing an output logic signal on said output line according to a relationship with said data signals received from said programmable input means, and programmable output means coupled between said output of said logic circuit means and said output line for selectively inverting said output logic signal.

Claim 16

A programmable logic circuit having a plurality of input lines for receiving data signals and an output line for providing a logic signal as a logic function of said data signals received, said programmable logic circuit comprising: a plurality of input stages, each input stage including: a first programmable input means coupled to said input lines for selectively inhibiting any number of said input lines and selectively inverting said data signals; a first logic means coupled to said first programmable input means for receiving said data signals and providing an output logic signal representative of the interrelationship of said data signals; a first programmable output means coupled to said first logic means for selectively inverting said output logic signal and providing same to an output of said input stage; and at least one output stage including: a second programmable input means coupled to said outputs of said plurality of input stages for selectively inhibiting any number of said outputs; a second logic means coupled to said second programmable input means for receiving said output logic signals from said second programmable input means and providing a second output logic signal representative of the interrelationship of said output logic signals; and a second programmable output means coupled between said second logic means and said output line of said logic circuit for selectively inverting said output logic signal.

Claim 17

A programmable logic circuit having a plurality of input lines for receiving data signals and an output line for providing a logic signal as a logic function of said data signals received, said programmable logic circuit comprising: a plurality of input stages, each input stage including: a first programmable input means coupled to said input lines for selectively inhibiting any number of said input lines and selectively inverting said data signals; a first logic means coupled to said first programmable input means for receiving said data signals and providing an output logic signal representative of the interrelationship of said data signals; a first programmable output means coupled to said first logic means for selectively inverting said output logic signal and providing same to an output of said input stage; and at least one output stage including: a second programmable input means coupled to said outputs of said plurality of input stages for selectively inhibiting any number of said outputs; a second logic means coupled to said second programmable input means for receiving said output logic signals from said second programmable input means and providing a second output logic signal representative of the interrelationship of said output logic signals; and a second programmable output means coupled between said second logic means and said output line of said logic circuit for selectively inverting said output logic signal.

Claim 18

A programmable logic circuit comprising: at least two programmable input stages, each having a first programmable number of input means for receiving data signals and at least one output means, wherein said input stage implements a first predetermined logic function on said data signals and provides the resulting logic signal at said output means, wherein each of said input means includes a first means for selectively inverting said logic signal applied thereto, and a programmable output stage having a second programmable number of input means coupled to said output means of said input stages for receiving a selected number of said logic signals from said input stages, said output stage implementing a second predetermined logic function on said logic signals.

Claim 19

A programmable logic circuit comprising: at least two programmable input stages, each having a first programmable number of input means for receiving data signals and at least one output means, wherein said input stage implements a first predetermined logic function on said data signals and provides the resulting logic signal at said output means, wherein each of said input means includes a first means for selectively inverting said logic signal applied thereto, and a programmable output stage having a second programmable number of input means coupled to said output means of said input stages for receiving a selected number of said logic signals from said input stages, said output stage implementing a second predetermined logic function on said logic signals.

Claim 20

The logic circuit of claim 12, wherein said output means of said programmable input stage includes a second means for selectively inverting said logic signal at said output means.

Claim 21

The logic circuit of claim 12, wherein said programmable output stage further includes an output means for selectively inverting said logic signal.

Claim 22

An integrated circuit having a plurality of circuit inputs for receiving data signals and a circuit output, said circuit including: a plurality of exclusive OR gates, each having a first and a second input and an output, said first input being programmably coupled to a voltage potential and said second input being coupled to a corresponding circuit input for receiving data signals, wherein the output of the respective exclusive OR gate may be selectively inverted; a plurality of OR gates, each having a first and a second input and an output, said first input being programmably coupled to a voltage potential and said second input being coupled to a corresponding one of said exclusive OR gate outputs wherein said OR gates may be selectively inhibited, and an AND gate having multiple inputs and an output, wherein said inputs are coupled to said outputs of said OR gates and said output is coupled to said circuit output.

Claim 23

An integrated circuit having a plurality of circuit inputs for receiving data signals and a circuit output, said circuit including: a plurality of exclusive OR gates, each having a first and a second input and an output, said first input being programmably coupled to a voltage potential and said second input being coupled to a corresponding circuit input for receiving data signals, wherein the output of the respective exclusive OR gate may be selectively inverted; a plurality of OR gates, each having a first and a second input and an output, said first input being programmably coupled to a voltage potential and said second input being coupled to a corresponding one of said exclusive OR gate outputs wherein said OR gates may be selectively inhibited, and an AND gate having multiple inputs and an output, wherein said inputs are coupled to said outputs of said OR gates and said output is coupled to said circuit output.

Claim 24

The integrated circuit of claim 15, further including an exclusive OR gate having a first and a second input and an output, said first input being programmably coupled to a voltage potential and said second input being coupled to said AND gate output and said output coupled to said circuit output, wherein said output of said exclusive OR gate may be selectively inverted.

Claim 25

An integrated circuit having a plurality of circuit inputs and a circuit output including: a plurality of NOR gates, each having a first input programmably coupled to a first voltage potential and a second input coupled to one of said plurality of circuit inputs, wherein said first input may be inhibited, and an additional NOR gate having multiple inputs coupled to respective outputs of said NOR gates, and an output coupled to said circuit output.

Claim 26

An integrated circuit having a plurality of circuit inputs and a circuit output including: a plurality of NOR gates, each having a first input programmably coupled to a first voltage potential and a second input coupled to one of said plurality of circuit inputs, wherein said first input may be inhibited, and an additional NOR gate having multiple inputs coupled to respective outputs of said NOR gates, and an output coupled to said circuit output.

Claim 27

The integrated circuit of claim 17, further comprising an exclusive OR gate having a first and a second input and an output, said first input being programmably coupled to said first voltage potential and said second input being coupled to said output of said additional NOR gate, wherein said output of said exclusive OR gate may be selectively inverted.

Claim 28

Method of programming data signals comprising: receiving concurrent independent data signals; selecting at least a plurality of said independent data signals; independently controlling a logic true value of each of said data signals; providing an output signal in accordance with a predetermined logic relationship of said data signals; and independently controlling a logic true value of said output signal.

Claim 29

Method of programming data signals comprising: receiving concurrent independent data signals; selecting at least a plurality of said independent data signals; independently controlling a logic true value of each of said data signals; providing an output signal in accordance with a predetermined logic relationship of said data signals; and independently controlling a logic true value of said output signal.