← Back to Patent Explorer
US4554640A Expired / Lapsed US ⏱️ 0.0 years remaining

Programmable array logic circuit with shared product terms

Assignee: Lattice Semiconductor Corp
•
Filing: 1984-01-30
•
Granted: 1985-11-19
•
Expires: 2004-01-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates. This allows the product terms to be shared between two outputs.

Inventors

  • 👤 Sing Y. Wong
  • 👤 John M. Birkner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 04:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 124 words
A programmable integrated logic circuit array comprising: (a) a plurality of groups of logical AND gates; (b) a plurality of logical OR gates; (c) a matrix of electrical conductor lines arranged in rows and columns comprising: (i) input lines, and (ii) AND gate input lines for each of the AND gates within said plurality of groups of logical AND gates; (d) connecting means for selectively connecting the outputs from individual ones of said AND gates to the inputs of one or the other, but not both, of a pair of logical OR gates from among said plurality of logical OR gates; and (e) means for selectively connecting input lines and AND gate input lines to program a desired logical output from said OR gates.
Claim 2
Dependent Claim 124 words
A programmable integrated logic circuit array comprising: (a) a plurality of groups of logical AND gates; (b) a plurality of logical OR gates; (c) a matrix of electrical conductor lines arranged in rows and columns comprising: (i) input lines, and (ii) AND gate input lines for each of the AND gates within said plurality of groups of logical AND gates; (d) connecting means for selectively connecting the outputs from individual ones of said AND gates to the inputs of one or the other, but not both, of a pair of logical OR gates from among said plurality of logical OR gates; and (e) means for selectively connecting input lines and AND gate input lines to program a desired logical output from said OR gates.
Claim 3
Dependent Claim 17 words
A programmable integrated logic circuit array as in claim 1 wherein said connecting means comprises fuseable links.
Claim 4
Dependent Claim 19 words
A programmable integrated logic circuit as in claim 1 wherein said OR gate pairs are adjacent to each other.
Claim 5
Dependent Claim 101 words
A programmable array of integrated logic circuitry comprising: (a) a plurality of AND gates, each AND gate having a plurality of inputs and an output; (b) a programmable matrix comprising a plurality of input lines and said inputs to said AND gates arranged in rows and columns; (c) a plurality of OR gates; (d) programmable electrical connections between the outputs of sub-pluralities of said AND gates and predetermined and select individual neighboring pairs of said OR gates; and (e) means for selectively connecting individual ones of said AND gate outputs to one, but not both, inputs of said OR gate pairs.
Claim 6
Dependent Claim 101 words
A programmable array of integrated logic circuitry comprising: (a) a plurality of AND gates, each AND gate having a plurality of inputs and an output; (b) a programmable matrix comprising a plurality of input lines and said inputs to said AND gates arranged in rows and columns; (c) a plurality of OR gates; (d) programmable electrical connections between the outputs of sub-pluralities of said AND gates and predetermined and select individual neighboring pairs of said OR gates; and (e) means for selectively connecting individual ones of said AND gate outputs to one, but not both, inputs of said OR gate pairs.

References Cited (Backward Citations)

US4037089A Cited
US3987286A Cited
US4041459A Cited
US4032894A Cited
US4084152A Cited
US4124899A Cited
US4124899B1 Cited
US4123669A Cited
US4488246A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-11-18 1989-05-20 1989-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-11-18 1993-05-20 1993-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-11-18 1997-05-20 1997-11-19 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag