US3602733A
Expired / Lapsed
US
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Three output level logic circuit
Assignee: Signetics Corp
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Filing: 1969-04-16
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Granted: 1971-08-31
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Expires: 1989-04-16
Abstract
Abstract A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.
Inventors
- 👤 Edward M Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
142 words
In a logic circuit having first and second signal-receiving input means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal-receiving input means and to said output terminal for selectively switching between first and second conditions in response to application of a signal to the first signal-receiving input means to provide first or second output levels on said output terminal, and second switching means connected to said second signal-receiving input means and to said first switching means to cause said first switching means to assume a third condition in response to the application of a signal to said second signal-receiving input means to provide a third output level at said output terminal, said output terminal exhibiting a high impedance relative to said first and second output levels.
Claim 2
Dependent Claim
142 words
In a logic circuit having first and second signal-receiving input means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal-receiving input means and to said output terminal for selectively switching between first and second conditions in response to application of a signal to the first signal-receiving input means to provide first or second output levels on said output terminal, and second switching means connected to said second signal-receiving input means and to said first switching means to cause said first switching means to assume a third condition in response to the application of a signal to said second signal-receiving input means to provide a third output level at said output terminal, said output terminal exhibiting a high impedance relative to said first and second output levels.
Claim 3
Dependent Claim
40 words
A logic circuit as in claim 1 where said output terminal at said first and second output levels serves as a current sink or current source and at said third output level said output terminal provides a high output impedance.
Claim 4
Dependent Claim
84 words
A logic circuit as in claim 1 in which said first switching means includes first and second output means coupled to said output terminal in which for one of said two output levels one of said output means is active and the other inactive and for said other of said two output levels the other of said output means is active and the one is inactive and in which for said third output level said second switching means inactivates both of said output means.
Claim 5
Dependent Claim
91 words
A logic circuit as in claim 3 in which said first and second output means includes first and second transistors respectively said first transistor being coupled to a third transistor and said second transistor being coupled to a fourth transistor, said second switching means when said logic circuit is in said third output level providing a low impedance path-shunting current from an input terminal of said third transistor to inactivate said first transistor and in addition shunting current from an output terminal of said fourth transistor to inactivate said second transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |