Array logic fabrication for use in pattern recognition equipments and the like

Claim 2

A fabrication arrangement for a measurement system including a plurality of measurement elements, each measurement element including a plurality of LSI chips, each chip comprising at least a pair of shift register portions serially connected, one portion being an array input portion and the other portion being a delay portion which does not provide an input to any array, the pair of portions providing a shift register entity on the chip, a programmable logic arry (PLA) section for forming part of a PLA entity in a measurement element, the PLA section having inputs connected to parallel outputs of the array input portion on the same chip, a plurality of latches, coupling means for connecting outputs of said latches to other inputs of the PLA section, a plurality of latch input pins, and means for respectively connecting the latch input pins to inputs of the latches, first interconnecting means for interconnecting corresponding outputs of the PLA sections extrnal to the chips within a measurement element, the first interconnecting means being also connected to predetermined latch input pins on selected chips in the same measurement element, the measurement element having feedback connections provided by the first interconnecting means along the chips, a signal terminal in the measurement system external to the measurement elements for receiving an input bit stream to be detected, input terminals of a first measurement element in the measurement system being connected to the signal terminal, an initial-delay shift register located external to the measurement elements in the measurement system, the initial-delay shift register containing a plurality of bit positions equal to the number of bit positions in the delay portion on a chip, an output of the initial-delay shift register connected to the input terminal of a second measurement element in the measurement system, whereby the input bit stream is directly inputted to the first measurement element but is delayed by the initial-delay shift register before being inputted to the second measurement element, and whereby the chips can be identically fabricated for both the first and second measurement elements.

Claim 3

A fabrication arrangement for a measurement system as defined in claim 1, the measurement system further including, second interconnecting means external to the measurement element for interconnecting the output of the first measurement element to a latch input pin on a chip in the second measurement element, and third interconnecting means external to the measurement element for interconnecting the output of the second measurement element to a latch input pin on a chip in the first measurement element, whereby the pair of measurement elements connected by the second and third connecting means comprise a subsystem of the measurement system.

Claim 4

The fabrication arrangement for a measurement system including a plurality of measurement elements, each measurement element including a plurality of LSI chips, each chip comprising at least a pair of shift register portions serially connected, one portion being an array input portion and the other portion being a delay portion which does not provide an output to any array, the pair of portions providing a shift register entity on a chip, an input pin on the chip connected to an input of the shift register entity to provide signals from a bit stream, a programmable logic array (PLA) section for forming part of a PLA entity in a measurement element, the PLA section having inputs connected to parallel outputs of the array input portion on the same chip, a plurality of latches, coupling means for connecting outputs of said latches to other inputs of the PLA section, a plurality of latch input pins, and means for respectively connecting the latch input pins to inputs of the latches, first interconnecting means for interconnecting corresponding outputs of the PLA sections external to the chips a measurement element, the first interconnecting means being also connected to predetermined latch input pins on selected chips in the same measurement element, the measurement element having feedback connections provided by the first interconnecting means among the chips, the plurality of chips of a measurement element being divided into halves as a first set and a second set of chips, an input terminal for each first set, and an input terminal for each second set, a signal terminal external to the measurement elements for receiving an input bit stream to be detected, a plurality of delay shift registers external to the chips, each with a number of shift positions equal to a delay portion on a chip, an input terminal of a first set of a first measurement element being connected to the signal terminal through a first delay shift register, a left/right shift register located external to the measurement elements in the measurement system, the left/right shift register containing a plurality of bit positions equal to one-half the number of bit positions in a bit stream frame to be detected, an input terminal of a second set in the first measurement element being connected to an output of the left/right shift register, another input terminal of a second set in the second measurement element being connected to the output of the left/right shift register through a second delay shift register, whereby the chips containing array portions can be identically fabricated for the measurement elements.

Claim 5

The fabrication arrangement for a measurement system including a plurality of measurement elements, each measurement element including a plurality of LSI chips, each chip comprising at least a pair of shift register portions serially connected, one portion being an array input portion and the other portion being a delay portion which does not provide an output to any array, the pair of portions providing a shift register entity on a chip, an input pin on the chip connected to an input of the shift register entity to provide signals from a bit stream, a programmable logic array (PLA) section for forming part of a PLA entity in a measurement element, the PLA section having inputs connected to parallel outputs of the array input portion on the same chip, a plurality of latches, coupling means for connecting outputs of said latches to other inputs of the PLA section, a plurality of latch input pins, and means for respectively connecting the latch input pins to inputs of the latches, first interconnecting means for interconnecting corresponding outputs of the PLA sections external to the chips a measurement element, the first interconnecting means being also connected to predetermined latch input pins on selected chips in the same measurement element, the measurement element having feedback connections provided by the first interconnecting means among the chips, the plurality of chips of a measurement element being divided into halves as a first set and a second set of chips, an input terminal for each first set, and an input terminal for each second set, a signal terminal external to the measurement elements for receiving an input bit stream to be detected, a plurality of delay shift registers external to the chips, each with a number of shift positions equal to a delay portion on a chip, an input terminal of a first set of a first measurement element being connected to the signal terminal through a first delay shift register, a left/right shift register located external to the measurement elements in the measurement system, the left/right shift register containing a plurality of bit positions equal to one-half the number of bit positions in a bit stream frame to be detected, an input terminal of a second set in the first measurement element being connected to an output of the left/right shift register, another input terminal of a second set in the second measurement element being connected to the output of the left/right shift register through a second delay shift register, whereby the chips containing array portions can be identically fabricated for the measurement elements.

Claim 6

The fabrication arrangement for a measurement system including measurement elements as defined in claim 3, the measurement system including an input terminal of a first set of a third measurement element being connected to the signal terminal, an input terminal of a first set in a fourth measurement element being connected to the signal terminal through a third delay shift register, a half-frame shift register having an input connected to the signal terminal, the half-frame shift register containing a plurality of bit positions equal to one-half the number of bit positions in a bit stream frame to be detected, an input terminal of a second set in the third measurement element being connected to an output of the half-frame shift register, an input terminal of a second set in the fourth measurement element being connected to the output of the half-frame shift register through a fourth delay shift register, whereby the chips containing array portions can be identically fabricated for the measurement elements.