Multiple function programmable arrays

Claim 2

A circuit for generating any arbitrary sequential function comprising an array logic block having input and output means, said array logic block comprising at least one two-dimensional array of identical, fixedly interconnected component modules, each of said component modules having memory means, wherein said circuit further comprises a single feedback path connecting the output of one of said arrays to said input means of said array logic block.

Claim 3

A circuit according to claim 1, wherein said component modules are connected in a tree configuration to form each of said arrays.

Claim 4

generating a first ordered sequence of signals corresponding to an information flow table representation of said sequential function,

Claim 5

generating a first ordered sequence of signals corresponding to an information flow table representation of said sequential function,

Claim 6

generating a fourth ordered sequence of signals corresponding to a minimized version of said implication graph representation of said sequential function, said minimized version comprising terms representative of the null set and identity set only, and

Claim 7

generating a fourth ordered sequence of signals corresponding to a minimized version of said implication graph representation of said sequential function, said minimized version comprising terms representative of the null set and identity set only, and

Claim 8

generating a minimized ordered sequence of signals for said leftmost column, said minimized version comprising terms representative of the null set and identity set only, and

Claim 9

generating a minimized ordered sequence of signals for said leftmost column, said minimized version comprising terms representative of the null set and identity set only, and

Claim 10

generating a different minimized ordered sequence of signals for said leftmost column, said minimized version comprising terms representative of the null set and identity set only, and

Claim 11

generating a different minimized ordered sequence of signals for said leftmost column, said minimized version comprising terms representative of the null set and identity set only, and

Claim 12

applying a logic 1 signal to each internal input terminal of each module of said leftmost column requiring an internal input signal corresponding to the identity set of said flow table different minimized version and applying a logical 0 signal to each internal input terminal of each moduLe of said leftmost column requiring an input signal corresponding to the null set, as characterized by said flow table minimized version of said sequential function.

Claim 13

applying a logic 1 signal to each internal input terminal of each module of said leftmost column requiring an internal input signal corresponding to the identity set of said flow table different minimized version and applying a logical 0 signal to each internal input terminal of each moduLe of said leftmost column requiring an input signal corresponding to the null set, as characterized by said flow table minimized version of said sequential function.

Claim 14

summing selected ones of a different set of minterms corresponding to said ordered sequence of signals corresponding to said implication graph minimized version of said sequential function.

Claim 15

summing selected ones of a different set of minterms corresponding to said ordered sequence of signals corresponding to said implication graph minimized version of said sequential function.

Claim 16

applying a logic 1 signal to each internal input term of each module of said leftmost column requiring an internal input signal corresponding to the identity set of said flow table minimized version and applying a logic 0 signal to each internal input terminal of each module of said leftmost column requiring an input signal corresponding to the null set as characterized by said flow table minimized version of said sequential function.

Claim 17

applying a logic 1 signal to each internal input term of each module of said leftmost column requiring an internal input signal corresponding to the identity set of said flow table minimized version and applying a logic 0 signal to each internal input terminal of each module of said leftmost column requiring an input signal corresponding to the null set as characterized by said flow table minimized version of said sequential function.

Claim 18

generating a second ordered sequence of signals corresponding to a minimized version of said first ordered sequence, said minimized version comprising terms representative of the null set and identity set only, and

Claim 19

generating a second ordered sequence of signals corresponding to a minimized version of said first ordered sequence, said minimized version comprising terms representative of the null set and identity set only, and

Claim 20

A circuit according to claim 1 wherein said arrays of component modules each comprise a four-neighbor rectangular arrangement of said component modules, said component modules being connected to form the rows and columns of said rectangular arrangement.

Claim 21

A circuit according to claim 3 wherein each of said component modules comprises a half-adder logic configuration.

Claim 22

interconnecting selected ones of the remaining row of 2n modules to the bottom row of said configuration corresponding to said second ordered sequence of signals.

Claim 23

interconnecting selected ones of the remaining row of 2n modules to the bottom row of said configuration corresponding to said second ordered sequence of signals.

Claim 24

A circuit according to claim 3 wherein each of said arrays further comprises a plurality of collector modules, said collector modules being connected to each other to form a row, and each of said collector modules being selectively connected to corresponding ones of said component modules appearing in an exterior row of said rectangular arrangement.

Claim 25

A circuit according to claim 5 wherein each of said component modules and each of said collector modules comprises a half-adder logic configuration.

Claim 26

A circuit for generating any arbitrary sequential switching function comprising at least one logic module array having input and output terminals, said array including a plurality of identical logic modules fixedly interconnected in a highly regular manner, each of said logic modules comprising logic circuitry and delay means, selected ones of said modules being located at an edge of a two-dimensional arrangement of said array, and means connected to said selected modules responsive to external stimuli, for programming said array to produce at its output terminals a specified function of the variables at its input terminals.

Claim 27

A circuit for generating any arbitrary sequential switching function comprising at least one logic module array having input and output terminals, said array including a plurality of identical logic modules fixedly interconnected in a highly regular manner, each of said logic modules comprising logic circuitry and delay means, selected ones of said modules being located at an edge of a two-dimensional arrangement of said array, and means connected to said selected modules responsive to external stimuli, for programming said array to produce at its output terminals a specified function of the variables at its input terminals.

Claim 28

A circuit according to claim 1 wherein certain ones of said modules of said logic array comprise error-detecting circuits.

Claim 29

A sequential switching circuit for generating desired sequences of circuit output signals in response to applied sequences of circuit input signals, said switching circuit comprising at least one tree array logic circuit comprising a plurality of component modules interconnected to form a tree configuration, said component modules each comprising logic circuitry and delay means, each of said tree array logic circuits thereby providing tree array output signals at one extremity of each of said tree configurations in response to tree array input signals applied at one or more of said component modules of said tree array logic circuit, means for applying said sequences of input signals to each component module of each of said tree array logic circuits, and means for applying constant-valued input signals to selected ones of said component modules.

Claim 30

A sequential switching circuit for generating desired sequences of circuit output signals in response to applied sequences of circuit input signals, said switching circuit comprising at least one tree array logic circuit comprising a plurality of component modules interconnected to form a tree configuration, said component modules each comprising logic circuitry and delay means, each of said tree array logic circuits thereby providing tree array output signals at one extremity of each of said tree configurations in response to tree array input signals applied at one or more of said component modules of said tree array logic circuit, means for applying said sequences of input signals to each component module of each of said tree array logic circuits, and means for applying constant-valued input signals to selected ones of said component modules.

Claim 31

The switching circuit of claim 9 wherein said tree array logic circuits are each arranged in a two-dimensional array and wherein said selected ones of said component modules are positioned adjacent an edge of said two-dimensional array.

Claim 32

The switching circuit of claim 10 further comprising means for applying output signals from at least one of said tree array logic circuits as feedback signals to selected ones of said component modules of selected ones of said tree array logic circuits.

Claim 33

A sequential switching circuit for generating desired sequences of circuit output signals in response to applied sequences of circuit input signal comprising at least one rectangular array logic circuit comprising a plurality of component modules interconnected to form a rectangular configuration, said component modules each comprising logic circuitry and delay means, each of said rectangular array logic circuits thereby providing rectangular array output signals at one extremity of each of said rectangular configurations in response to rectangular array input signals applied at one or more of said component modules of said rectangular array logic circuit, means for applying said sequences of input signals to each component module of each of said rectangular array logic circuits, means for applying constant-valued input signals to selected ones of said component modules, and means for selectively connecting selected ones of said component modules to other selected ones of said component modules.

Claim 34

A sequential switching circuit for generating desired sequences of circuit output signals in response to applied sequences of circuit input signal comprising at least one rectangular array logic circuit comprising a plurality of component modules interconnected to form a rectangular configuration, said component modules each comprising logic circuitry and delay means, each of said rectangular array logic circuits thereby providing rectangular array output signals at one extremity of each of said rectangular configurations in response to rectangular array input signals applied at one or more of said component modules of said rectangular array logic circuit, means for applying said sequences of input signals to each component module of each of said rectangular array logic circuits, means for applying constant-valued input signals to selected ones of said component modules, and means for selectively connecting selected ones of said component modules to other selected ones of said component modules.

Claim 35

The switching circuit of claim 12 further comprising means for applying output signals of one of said rectangular array logic circuits as a feedback signal to selected ones of said component modules of selected ones of said rectangular array logic circuits.

Claim 36

The switching circuit of claim 13 wherein said rectangular array logic circuit is characterized by having a four-neighbor array configuration.

Claim 37

The switching circuit of claim 13 wherein said component modules of said rectangular array logic circuit each comprise a half-adder logic configuration.

Claim 38

In a programmable finite state machine for realizing sequential functions, said machine having memory n, said machine further having at least one array of (n+1) by 2n functionally identical logic circuit modules, n by 2n of which are arranged in a regularly interconnected two-dimensional rectangular configuration having n rows of 2n modules, said configuration having a left and right side, a top and bottom, with the output signals of a given module applying input signals to adjacent modules, one of said adjacent modules located to the right of and one of said adjacent modules located below said given module, the method of programming said machine comprising the steps of

Claim 39

In a programmable finite state machine for realizing sequential functions, said machine having memory n, said machine further having at least one array of (n+1) by 2n functionally identical logic circuit modules, n by 2n of which are arranged in a regularly interconnected two-dimensional rectangular configuration having n rows of 2n modules, said configuration having a left and right side, a top and bottom, with the output signals of a given module applying input signals to adjacent modules, one of said adjacent modules located to the right of and one of said adjacent modules located below said given module, the method of programming said machine comprising the steps of

Claim 40

The method of realizing sequential functions according to claim 16 further comprising the steps of

Claim 41

In a finite state machine for realizing sequential functions, said machine having at least one array of functionally identical logic circuit modules, said modules being arranged in a regularly interconnected two-dimensional tree configuration having columns arranged from left to right, each of said modules having a number of external input terminals and a number of internal input terminals, the leftmost column having the largest number of said modules and the rightmost column having the least, the output from the modules of each of said columns, except the rightmost column, forming the internal input signals to the modules of the adjacent column to the right, said leftmost column having constant-valued internal input signals only, the method of programming said machine comprising

Claim 42

In a finite state machine for realizing sequential functions, said machine having at least one array of functionally identical logic circuit modules, said modules being arranged in a regularly interconnected two-dimensional tree configuration having columns arranged from left to right, each of said modules having a number of external input terminals and a number of internal input terminals, the leftmost column having the largest number of said modules and the rightmost column having the least, the output from the modules of each of said columns, except the rightmost column, forming the internal input signals to the modules of the adjacent column to the right, said leftmost column having constant-valued internal input signals only, the method of programming said machine comprising

Claim 43

The method of realizing sequential functions according to claim 18 further comprising the steps of