Mos data bus control circuitry

Claim 2

A semiconductor circuit including a first control signal input, a second control signal input, a first conductor adapted to having an output signal coupled thereto, a data conductor within said semiconductor circuit adapted to having a data signal applied thereto, and logic circuitry coupled to said first control signal input for generating an internal control signal, said semiconductor circuit comprising data output circuit means coupled to said logic circuitry and to said first conductor and to said data conductor and to said second control signal input for actively holding a data signal on said first conductor during a cycle in which a first signal is applied to said first control signal input in response to an edge of a second control signal applied to said second control signal input.

Claim 3

A semiconductor circuit including a first control signal input, a second control signal input, a first conductor adapted to having an output signal coupled thereto, a data conductor within said semiconductor circuit adapted to having a data signal applied thereto, and logic circuitry coupled to said first control signal input for generating an internal control signal, said semiconductor circuit comprising data output circuit means coupled to said logic circuitry and to said first conductor and to said data conductor and to said second control signal input for actively holding a data signal on said first conductor during a cycle in which a first signal is applied to said first control signal input in response to an edge of a second control signal applied to said second control signal input and for allowing said first conductor to electrically float except during coincidence of said first control signal and said second control signal.

Claim 4

A semiconductor circuit including a first control signal input, a second control signal input, a first conductor adapted to having an output signal coupled thereto, a data conductor within said semiconductor circuit adapted to having a data signal applied thereto, and logic circuitry coupled to said first control signal input for generating an internal control signal, said semiconductor circuit comprising data output circuit means coupled to said logic circuitry and to said first conductor and to said data conductor and to said second control signal input for actively holding a data signal on said first conductor during a cycle in which a first signal is applied to said first control signal input in response to an edge of a second control signal applied to said second control signal input and for allowing said first conductor to electrically float except during coincidence of said first control signal and said second control signal.

Claim 5

The semiconductor circuit as recited in claim 2 further including delay circuit means coupled between said second control signal input and said data output circuit means for controlling coupling of said data signal to said data output circuit means so that said first conductor is allowed to electrically float before said data signal is coupled to said data output circuit means, in response to a signal applied to said second control signal input.

Claim 6

The semiconductor circuit as recited in claim 2 wherein said data output circuit means includes MOS output driver circuit means coupled to said first conductor for holding a logical 1 or a logical 0 level on said first conductor or allowing said first conductor to electrically float, in response to signals on said first control signal input, said second control signal input or said data conductor.

Claim 7

The semiconductor circuit as recited in claim 4 wherein said MOS output driver circuit means includes a pull-up MOSFET coupled between a first voltage conductor and said first conductor having its gate connected to other circuitry also in said data output circuit means and a pull-down MOSFET coupled between said first conductor and a second voltage conductor having its gate connected to said other circuitry.

Claim 8

The semiconductor circuit as recited in claim 5 wherein said other circuitry includes first and second MOSFET NOR gates, said first and second MOSFET NOR gates each having an input connected to a common node, said first MOSFET NOR gate having an input coupled to said data conductor by coupling circuit means and having its output connected to an input of said second MOSFET NOR gate and to said pull-down MOSFET, said second MOSFET NOR gate having its output connected to the gate of said puLl-up MOSFET.

Claim 9

The semiconductor circuit as recited in claim 6 including an inverter having an input coupled to said second control signal input, a coupling MOSFET having one main electrode coupled to said logic circuitry and having its gate connected to the output of said inverter and having its other main electrode connected to an input of a NOR gate, said NOR gate having its other input connected to the output of said inverter and having its output connected to an input of a second inverter, said second inverter having its output connected to said node.

Claim 10

A semiconductor circuit as recited in claim 7 further including a delay circuit including two cascaded inverters coupled between an enable circuit of said semiconductor circuit and a gate electrode of said second coupling MOSFET coupling said second input of said first MOSFET NOR gate and said second data conductor, said enable circuit being coupled to said second control signal input and said logic circuitry.

Claim 11

The semiconductor circuit as recited in claim 2 wherein said logic circuitry also generates said data signal in response to an input signal applied to said first conductor.

Claim 12

A semiconductor circuit comprising: logic circuitry means coupled to a first control signal input for generating a read/write signal at a first node; a first MOSFET having a gate connected to a first clock input coupling said first node to a second node; a second MOSFET coupling said second node to a third node, said second MOSFET having its gate connected to a fourth node; a first NOR gate having two inputs connected, respectively, to said third and fourth nodes and having an output connected to a fifth node; a first inverter having an input connected to said fifth node and an output connected to a sixth node; a TRI-STATE output circuit having an input connected to said sixth node and also having an output node; and a coupling circuit coupling an internal data conductor to another input of said TRI-STATE output circuit, said internal data conductor being coupled to said logic circuitry means for having a control signal generated thereon by said logic circuitry means, said TRI-STATE output circuit being a circuit for providing a high output impedance corresponding to one configuration of said inputs of said TRISTATE output circuit and for providing a low output impedance during another voltage configuration of said inputs of said TRI-STATE output circuit.

Claim 13

A semiconductor circuit comprising: logic circuitry means coupled to a first control signal input for generating a read/write signal at a first node; a first MOSFET having a gate connected to a first clock input coupling said first node to a second node; a second MOSFET coupling said second node to a third node, said second MOSFET having its gate connected to a fourth node; a first NOR gate having two inputs connected, respectively, to said third and fourth nodes and having an output connected to a fifth node; a first inverter having an input connected to said fifth node and an output connected to a sixth node; a TRI-STATE output circuit having an input connected to said sixth node and also having an output node; and a coupling circuit coupling an internal data conductor to another input of said TRI-STATE output circuit, said internal data conductor being coupled to said logic circuitry means for having a control signal generated thereon by said logic circuitry means, said TRI-STATE output circuit being a circuit for providing a high output impedance corresponding to one configuration of said inputs of said TRISTATE output circuit and for providing a low output impedance during another voltage configuration of said inputs of said TRI-STATE output circuit.

Claim 14

The semiconductor circuit as recited in claim 10 wherein said coupling circuit includes a third MOSFET coupling said internal data conductor to a seventh node having a gate connected to said first clock input and further includes a fourth MOSFET coupling said seventh node to said other input of said TRI-STATE circuit, said fourth MOSFET having a gate connected to a control circuit in said semiconductor circuit.

Claim 15

The semiconductor circuit as recited in claim 11 wherein said control circuit includes a delay circuit having an input connected to said fourth node.

Claim 16

The semiconductor circuit as recited in claim 10 wherein said semiconductor circuit is part of an integrated circuit micro-processor chip.