US5220213A
Expired / Lapsed
US
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Programmable application specific integrated circuit and logic cell therefor
Assignee: QuickLogic Corp
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Filing: 1992-03-06
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Granted: 1993-06-15
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Expires: 2012-03-06
Abstract
Abstract A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.
Inventors
- 👤 Andrew K. Chan
- 👤 Hua-Thye Chua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17724; H03K19/17728; H03K19/1733; H03K19/1737; H03K19/17704
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
157 words
A logic cell for a programmable application specific integrated circuit, comprising: a first logic gate; a second logic gate; a third logic gate; a first multiplexer having one data input from an output of said first logic gate, another data input from an output of said second logic gate, and a select input from an output of said third logic gate; a fourth logic gate; a fifth logic gate; a second multiplexer having one data input from an output of said fourth logic gate, another data input from an output of said fifth logic gate, and a select input from an output of said third logic gate; a sixth logic gate; a third multiplexer having one data input from an output of said first multiplexer, another data input from an output of said second multiplexer, and a select input from said sixth logic gate; and a flipflop having an input from an output of said third multiplexer.
Claim 2
Dependent Claim
157 words
A logic cell for a programmable application specific integrated circuit, comprising: a first logic gate; a second logic gate; a third logic gate; a first multiplexer having one data input from an output of said first logic gate, another data input from an output of said second logic gate, and a select input from an output of said third logic gate; a fourth logic gate; a fifth logic gate; a second multiplexer having one data input from an output of said fourth logic gate, another data input from an output of said fifth logic gate, and a select input from an output of said third logic gate; a sixth logic gate; a third multiplexer having one data input from an output of said first multiplexer, another data input from an output of said second multiplexer, and a select input from said sixth logic gate; and a flipflop having an input from an output of said third multiplexer.
Claim 3
Dependent Claim
43 words
An apparatus as in claim 1, wherein: said first, second, fourth and fifth logic gates are AND gates; said third and sixth logic gates are AND gates; said first, second and third multiplexers are 2:1 multiplexers; and said flipflop is a delay flipflop.
Claim 4
Dependent Claim
267 words
A logic cell for a programmable application specific integrated circuit, comprising: a first logic gate; a second logic gate; a third logic gate, said third logic gate having a first input and a second input, said first input of said third logic gate being connected to a first data node; a fourth logic gate, said fourth logic gate having an output, said output of the fourth logic gate being connected to said second input of said third logic gate; a first multiplexer having one data input from an output of said first logic gate, another data input from an output of said second logic gate, and a select input from an output of said third logic gate; a fifth logic gate; a sixth logic gate; a second multiplexer having one data input from an output of said fifth logic gate, another data input from an output of said sixth logic gate, and a select input from an output of said third logic gate; a seventh logic gate, said seventh logic gate having a first input and a second input, said first input being connected to a second data node; an eighth logic gate, said eighth logic gate having an output, said output of said eighth logic gate being connected to said second input of said seventh logic gate; a third multiplexer having one data input from an output of said first multiplexer, another data input from an output of said second multiplexer, and a select input from an output of said seventh logic gate; and a flipflop having an input from an output of said third multiplexer.
Claim 5
Dependent Claim
267 words
A logic cell for a programmable application specific integrated circuit, comprising: a first logic gate; a second logic gate; a third logic gate, said third logic gate having a first input and a second input, said first input of said third logic gate being connected to a first data node; a fourth logic gate, said fourth logic gate having an output, said output of the fourth logic gate being connected to said second input of said third logic gate; a first multiplexer having one data input from an output of said first logic gate, another data input from an output of said second logic gate, and a select input from an output of said third logic gate; a fifth logic gate; a sixth logic gate; a second multiplexer having one data input from an output of said fifth logic gate, another data input from an output of said sixth logic gate, and a select input from an output of said third logic gate; a seventh logic gate, said seventh logic gate having a first input and a second input, said first input being connected to a second data node; an eighth logic gate, said eighth logic gate having an output, said output of said eighth logic gate being connected to said second input of said seventh logic gate; a third multiplexer having one data input from an output of said first multiplexer, another data input from an output of said second multiplexer, and a select input from an output of said seventh logic gate; and a flipflop having an input from an output of said third multiplexer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-14 | 1996-12-14 | 1997-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-14 | 2000-12-14 | 2001-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-14 | 2004-12-14 | 2005-06-15 | $7700.00 | Window Closed / Lapsed |