Reconfigurable programmable interconnect architecture

Claim 2

In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of modules placed in an array, the modules having connection nodes, a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments is connected to at least one of said connection nodes, a plurality of reconfigurable elements, each of said reconfigurable elements having two main terminals, said main terminals connected between selected ones of said wiring segments comprising one of said channels, each of said reconfigurable elements further including a control terminal, configuring means, connected to said control terminals, for selectively rendering said reconfigurable elements conductive or non-conductive between said two main terminals, series-pass transistors connecting selected adjacent ones of said segments, each of said series-pass transistors having a control element, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

Claim 3

The electrically programmable interconnect architecture of claim 1 wherein at least one of said wiring channels lies in a direction substantially non-parallel to the remainder of said wiring channels and is disposed in a layer electrically isolated from the layer containing said remainder of wiring channels, forming intersections.

Claim 4

The electrically-programmable interconnect architecture of claim 2, further comprising: reconfigurable elements connected between selected ones of those wiring segments of said sets of wiring channels which intersect each other at said intersections.

Claim 5

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes, a plurality of first wiring channels running in a first direction, at least one of which is connected to at least one of said connection nodes, at least one of said plurality of first wiring channels including at least two adjacent wiring segments, a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, intersecting said first wiring channels at at least one intersection, at least one of said plurality of second wiring channels including at least two adjacent wiring segments one of which forms said intersection with one of said wiring segments in said plurality of said first wiring channels, a plurality of reconfigurable elements, each having two main terminals, connected between at least one pair of the intersecting wiring segments series-pass transistors connecting selected adjacent and intersecting ones of said segments, each of said series-pass transistors having a control element, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

Claim 6

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes, a plurality of first wiring channels running in a first direction, at least one of which is connected to at least one of said connection nodes, at least one of said plurality of first wiring channels including at least two adjacent wiring segments, a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, intersecting said first wiring channels at at least one intersection, at least one of said plurality of second wiring channels including at least two adjacent wiring segments one of which forms said intersection with one of said wiring segments in said plurality of said first wiring channels, a plurality of reconfigurable elements, each having two main terminals, connected between at least one pair of the intersecting wiring segments series-pass transistors connecting selected adjacent and intersecting ones of said segments, each of said series-pass transistors having a control element, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

Claim 7

The array logic circuit according to claim 4, in which one or more of said wiring channels comprises a series of wiring segments and further including additional ones of said reconfigurable elements having two main terminals connected between adjacent ones of said wiring segments.

Claim 8

The array logic circuitry according to claim 4 in which substantially all of said first and second wiring channels comprise a series of wiring segments, each of said wiring segments having a length equal to at least the smaller of the length or width of one logic module.

Claim 9

The array logic circuit according to claim 5 in which wiring segments of said first wiring channels have a length equivalent to the length of two logic modules and the wiring segments of said second wiring channels have a length equivalent to the width of three logic modules.

Claim 10

The array logic circuit according to claim 5, in which at least two of adjacent ones of said wiring segments forming a wiring channel are joined in series at their ends by series pass transistors having control elements.

Claim 11

The logic circuit according to claim 8 further comprising selection circuitry connected to the control element of each series-pass transistor in order to cause said series-pass transistor to conduct or not to conduct current between the wiring segments to which it is electrically connected.

Claim 12

The logic circuit according to claim 8 further comprising select transistors electrically connected to a middle wiring segment of each wiring channel which, when biased to conduct, connects the middle wiring segment to a selected potential.

Claim 13

The logic circuit according to claim 9 further comprising: circuitry, connectable to selected ones of said wiring segments by said selection circuitry for providing preselected voltage to cause selected ones of said reconfigurable elements to conduct.

Claim 14

The logic circuit according to claim 10 further comprising: circuitry, connectable to selected ones of said wiring segments by said selection circuitry for providing preselected voltages to cause selected ones of said reconfigurable elements to conduct.

Claim 15

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including at least two wiring segments, at least one wiring segment of one wiring channel connected to at least one of said connection nodes, at least one of said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, at least two of said wiring segments of at least one of said wiring channels being joined in series by series-pass transistors, at least two of said wiring segments of at least one of said wiring channels being joined in series by reconfigurable elements, at least two of said wiring segments that intersect each other being connected by two main terminals of reconfigurable elements, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 16

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including at least two wiring segments, at least one wiring segment of one wiring channel connected to at least one of said connection nodes, at least one of said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, at least two of said wiring segments of at least one of said wiring channels being joined in series by series-pass transistors, at least two of said wiring segments of at least one of said wiring channels being joined in series by reconfigurable elements, at least two of said wiring segments that intersect each other being connected by two main terminals of reconfigurable elements, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 17

In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of modules placed in an array, the modules having connection nodes, a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments in at least one wiring channel is connected to at least one of said connection nodes, a plurality of EPROM memory transistors, each of said EPROM memory transistors having a source and a drain, said source and said drain connected between selected ones of said wiring segments comprising one of said channels, said each of EPROM memory transistors further including a control gate, configuring means, connected to said sources, drains, and control gates of said EPROM memory transistors, for selectively rendering said EPROM memory transistors non-conductive.

Claim 18

In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of modules placed in an array, the modules having connection nodes, a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments in at least one wiring channel is connected to at least one of said connection nodes, a plurality of EPROM memory transistors, each of said EPROM memory transistors having a source and a drain, said source and said drain connected between selected ones of said wiring segments comprising one of said channels, said each of EPROM memory transistors further including a control gate, configuring means, connected to said sources, drains, and control gates of said EPROM memory transistors, for selectively rendering said EPROM memory transistors non-conductive.

Claim 19

The electrically programmable interconnect architecture of claim 14 wherein at least one of said wiring channels lies in a direction substantially non-parallel to the remainder of said wiring channels and is disposed in a layer electrically isolated from the layer containing said remainder of wiring channels, forming intersections.

Claim 20

The electrically-programmable interconnect architecture of claim 15, further comprising: EPROM memory transistors joining selected ones of those wiring segments of said sets of wiring channels which intersect each other at said intersections.

Claim 21

The electrically-programmable interconnect architecture according to claim 14, further comprising: series-pass transistors connecting selected adjacent and intersecting ones of said segments, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

Claim 22

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes; a plurality of first wiring channels running in a first direction, said first wiring channels containing a plurality of wiring segments, at least one of said wiring segments connected to at least one of said connection nodes a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, intersecting said first wiring channels at intersections, a plurality of EPROM memory transistors each having a source and drain connected between at least one pair of the intersecting wiring channels.

Claim 23

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes; a plurality of first wiring channels running in a first direction, said first wiring channels containing a plurality of wiring segments, at least one of said wiring segments connected to at least one of said connection nodes a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, intersecting said first wiring channels at intersections, a plurality of EPROM memory transistors each having a source and drain connected between at least one pair of the intersecting wiring channels.

Claim 24

The array logic circuitry according to claim 18 in which substantially all of said first and second wiring channels comprise a series of wiring segments, each of said wiring segments having a length equal to at least the smaller of the length or width of one logic module.

Claim 25

The array logic circuit according to claim 18 in which wiring segments of said first wiring channels have a length equivalent to the length of two logic modules and the wiring segments of said second wiring channels have a length equivalent to the width of three logic modules.

Claim 26

The array logic circuit according to claim 18, in which at least two of adjacent ones of said wiring segments forming a wiring channel are joined in series at their ends by series pass transistors having control elements.

Claim 27

The logic circuit according to claim 21 further comprising selection circuitry connected to the control element of each series-pass transistor in order to cause said series-pass transistor to conduct or not to conduct current between the wiring segments to which it is electrically connected.

Claim 28

The logic circuit according to claim 21 further comprising select transistors electrically connected to a middle wiring segment of each wiring channel which, when biased to conduct, connects the middle wiring segment to a selected potential.

Claim 29

The logic circuit according to claim 21 further comprising: circuitry, connectable to selected ones of said wiring segments by said selection circuitry for providing preselected voltage to program selected ones of said EPROM memory transistors.

Claim 30

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in one of said channels connected to at least one of said connection nodes, at least one of said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments that intersect each other being connected by EPROM memory transistors, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 31

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in one of said channels connected to at least one of said connection nodes, at least one of said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments that intersect each other being connected by EPROM memory transistors, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 32

In a programmable array logic circuit comprising a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, each set of wiring channels having at least one wiring channel comprising at least two wiring segments, at least one of said wiring segments connected to at least one of said connection nodes, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments in said logic circuit being joined in series by EPROM memory transistors, at least two of said wiring segments that intersect each other being connected by EPROM memory transistors, programming circuitry connected to the control elements of said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct, a method of programming selected ones of said EPROM memory transistors comprising the steps of: (a) preselecting a group of series-pass transistors to be biased to conduct such that a first current path will exist from a source of a first potential to the sources of each of said selected EPROM memory transistors and a second current path will exist from a source of a second potential to the drains of each of said selected EPROM memory transistors when said preselected series-pass transistors are biased, (b) biasing said group of series-pass transistors to conduct, and (c) applying said first potential to the sources of each of said EPROM memory transistors, applying said second potential to the drains of each of said EPROM memory transistors, and applying said first potential to the control gates of each of said EPROM memory transistors.

Claim 33

In a programmable array logic circuit comprising a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, each set of wiring channels having at least one wiring channel comprising at least two wiring segments, at least one of said wiring segments connected to at least one of said connection nodes, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments in said logic circuit being joined in series by EPROM memory transistors, at least two of said wiring segments that intersect each other being connected by EPROM memory transistors, programming circuitry connected to the control elements of said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct, a method of programming selected ones of said EPROM memory transistors comprising the steps of: (a) preselecting a group of series-pass transistors to be biased to conduct such that a first current path will exist from a source of a first potential to the sources of each of said selected EPROM memory transistors and a second current path will exist from a source of a second potential to the drains of each of said selected EPROM memory transistors when said preselected series-pass transistors are biased, (b) biasing said group of series-pass transistors to conduct, and (c) applying said first potential to the sources of each of said EPROM memory transistors, applying said second potential to the drains of each of said EPROM memory transistors, and applying said first potential to the control gates of each of said EPROM memory transistors.

Claim 34

In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of modules placed in an array, the modules having connection nodes, a plurality of sets of wiring channels, at least some o said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments is connected to at least one of said connection nodes, a plurality of EEPROM memory transistors, each of said EEPROM memory transistors having a source and a drain, said source and said drain connected between selected ones of said wiring segments, each of said EEPROM memory transistors further including a control gate, configuring means, connected to said sources, drains and control gates of said EEPROM memory transistors, for selectively rendering said EEPROM memory transistors conductive and nonconductive.

Claim 35

In an integrated circuit, an electrically programmable interconnect architecture, comprising: a plurality of modules placed in an array, the modules having connection nodes, a plurality of sets of wiring channels, at least some o said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments is connected to at least one of said connection nodes, a plurality of EEPROM memory transistors, each of said EEPROM memory transistors having a source and a drain, said source and said drain connected between selected ones of said wiring segments, each of said EEPROM memory transistors further including a control gate, configuring means, connected to said sources, drains and control gates of said EEPROM memory transistors, for selectively rendering said EEPROM memory transistors conductive and nonconductive.

Claim 36

The electrically programmable interconnect architecture of claim 27 wherein at least one of said wiring channels lies in a direction substantially non-parallel to the remainder of said wiring channels and is disposed in a layer electrically isolated from the layer containing said remainder of wiring channels, forming intersections.

Claim 37

The electrically-programmable interconnect architecture of claim 28, further comprising: EEPROM memory transistors joining selected ones of those wiring segments of said sets of wiring channels which intersect each other at said intersections.

Claim 38

The electrically-programmable interconnect architecture according to claim 27, further comprising: series-pass transistors connecting selected adjacent and intersecting ones of said segments, and selection circuitry connected to the control element of each of said series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

Claim 39

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes; a plurality of first wiring channels running in a first direction, said first wiring channels containing at least two wiring segments, at least one said wiring segments connected to at least one of said connection nodes; a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, said second wiring channels containing at least two wiring segments at least one of said wiring segments in said plurality of first wiring channels intersecting at least one of said wiring segments in said second plurality of wiring channels at intersections, a plurality of EEPROM memory transistors having sources and drains connecting at least one pair of the intersecting wiring segments.

Claim 40

A user-programmable array logic circuit, comprising: a plurality of logic modules placed on a substrate, the logic modules each having connection nodes; a plurality of first wiring channels running in a first direction, said first wiring channels containing at least two wiring segments, at least one said wiring segments connected to at least one of said connection nodes; a plurality of second wiring channels running in a second direction and disposed in a layer electrically isolated from the layer containing said first wiring channels, said second wiring channels containing at least two wiring segments at least one of said wiring segments in said plurality of first wiring channels intersecting at least one of said wiring segments in said second plurality of wiring channels at intersections, a plurality of EEPROM memory transistors having sources and drains connecting at least one pair of the intersecting wiring segments.

Claim 41

The array logic circuitry according to claim 31 in which substantially all of said first and second wiring channels comprise a series of wiring segments of at least the smaller of the length or width of one logic module.

Claim 42

The array logic circuit according to claim 31 in which wiring segments of said first wiring channels have a length equivalent to the length of two logic modules and the wiring segments of said second wiring channels have a length equivalent to the width of three logic modules.

Claim 43

The array logic circuit according to claim 31, in which at least two of adjacent ones of said wiring segments forming a wiring channel are joined in series at their ends by series pass transistors having control elements.

Claim 44

The logic circuit according to claim 34 further comprising selection circuitry connected to the control element of each series-pass transistor in order to cause said series-pass transistor to conduct or not to conduct current between the wiring segments to which it is electrically connected.

Claim 45

The logic circuit according to claim 34 further comprising select transistors electrically connected to a middle wiring segment of each wiring channel which, when biased to conduct, connects the middle wiring segment to a selected potential.

Claim 46

The logic circuit according to claim 35 further comprising: circuitry, connectable to selected ones of said wiring segments by said selection circuitry for providing preselected voltage to render conductive selected ones of said EEPROM memory transistors.

Claim 47

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in said circuit connected to at least one of said connection nodes, at least one said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments that intersect each other being connected by EEPROM memory transistors, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 48

A programmable array logic circuit, comprising: a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in said circuit connected to at least one of said connection nodes, at least one said wiring channels being in a direction substantially non-parallel to other ones of said wiring channels, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments that intersect each other being connected by EEPROM memory transistors, circuitry connected to said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct.

Claim 49

In a programmable array logic circuit comprising a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in said circuit connected to at least one of said connection nodes, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments of each wiring channel being joined in series by EEPROM memory transistors, at least two of said wiring segments intersecting each other and connected by EEPROM memory transistors, programming circuitry connected to the control elements of said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct, a method of rendering conductive a selected EEPROM memory transistor comprising the steps of: (a) preselecting a group of series-pass transistors to be biased to conduct such that a first current path will exist from a source of a first potential to the sources of each of said selected EEPROM memory transistors and a second current path will exist from a source of a second potential to the drains of each of said selected EEPROM memory transistors when said preselected series-pass transistors are biased, (b) biasing said group of series-pass transistors to conduct, and (c) applying said first potential to the sources of each of said selected EEPROM memory transistors, applying said second potential to the drains of each of said selected EEPROM memory transistors, and applying said first potential to the control gates of each of said selected EEPROM transistors.

Claim 50

In a programmable array logic circuit comprising a plurality of logic modules placed in an array, said logic modules each having connection nodes, a plurality of sets of wiring channels, at least one of said wiring channels including a plurality of wiring segments, at least one of said wiring segments in said circuit connected to at least one of said connection nodes, the wiring segments of at least one of the wiring channels being joined in series by series-pass transistors, at least two of said wiring segments of each wiring channel being joined in series by EEPROM memory transistors, at least two of said wiring segments intersecting each other and connected by EEPROM memory transistors, programming circuitry connected to the control elements of said series-pass transistors capable of selectively biasing said series-pass transistors to cause them to conduct or not to conduct, a method of rendering conductive a selected EEPROM memory transistor comprising the steps of: (a) preselecting a group of series-pass transistors to be biased to conduct such that a first current path will exist from a source of a first potential to the sources of each of said selected EEPROM memory transistors and a second current path will exist from a source of a second potential to the drains of each of said selected EEPROM memory transistors when said preselected series-pass transistors are biased, (b) biasing said group of series-pass transistors to conduct, and (c) applying said first potential to the sources of each of said selected EEPROM memory transistors, applying said second potential to the drains of each of said selected EEPROM memory transistors, and applying said first potential to the control gates of each of said selected EEPROM transistors.