High speed programmable logic architecture

Claim 1

A routing structure for a programmable logic circuit, the logic circuit including logic cells in which logic functions are performed, the routing structure comprising: a set of input lines for supplying signals to be processed by the logic cells, the input lines extending generally in a first direction; a set of output lines for receiving signals which have been processed by the logic cells, the output lines extending generally in a second direction not parallel to the first direction to cause the input and output lines to cross in junction regions; wherein each of the junction regions includes a plurality of controllable active driver circuits individual ones of which are connected between selected ones of the set of output lines and selected ones of the set of input lines to enable signals present on the output lines to be placed on desired ones of the set of input lines, the controllable active driver circuits having outputs nodes directly driving the input lines to which the controllable active driver circuit output nodes are connected; and wherein each of the controllable active driver circuits comprises a buffer circuit capable of being placed in at least an active state in which the controllable active driver circuit replicates a signal supplied to it and a passive state in which the controllable active driver circuit presents a high impedance between its input and output.