US5256918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic circuit
Assignee: Toshiba Corp
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Filing: 1992-02-21
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Granted: 1993-10-26
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Expires: 2012-02-21
Abstract
Abstract A programmable logic circuit has a data transfer circuit, fundamental programmable logic circuits, programmable wiring circuits, a decoder circuit, and an input/output circuit. The data transfer circuit outputs serial program data in a parallel manner. Each of the fundamental programmable logic circuits includes first data storage sections arranged in a matrix pattern. The signal output states of these first data storage sections are programmed in accordance with parallel data supplied from the data transfer circuit, and a logic circuit pattern is programmed in accordance with at least outputs of the first data storage sections. The programmable wiring circuits are arranged in adjacent to the fundamental programmable logic circuits and provide connection lines between the fundamental programmable logic circuits. Each of the programmable wiring circuits includes second data storage sections arranged in a matrix pattern. The signal output states of these second data storage sections are programmed in accordance with the parallel data supplied from the data transfer circuit, and switches located between the connection lines are selected or controlled in accordance with outputs of the second storage sections. The decoder circuit causes the first and second storage sections to store data output from the data transfer circuit in response to address designation.
Inventors
- 👤 Hiroaki Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A programmable logic circuit comprising: a data transfer circuit for outputting serial program data in a parallel manner; a plurality of fundamental programmable logic circuits each including first data storage sections arranged in a matrix pattern, said first data storage sections having signal output states which are programmed in accordance with parallel data supplied from the data transfer circuit, and a logic circuit pattern being programmed in accordance with at least outputs of the first data storage sections; a plurality of programmable wiring means, arranged in adjacent to the fundamental programmable logic circuits, for providing connection lines between the fundamental programmable logic circuits, said programmable wiring means including second data storage sections arranged in a matrix pattern, said second data storage sections having signal output states which are programmed in accordance with the parallel data supplied from the data transfer circuit, and switches located between the connection lines being selected or controlled in accordance with outputs of the second storage sections; a decoder circuit for causing the first and second storage sections to store data output from the data transfer circuit in response to address designation; and an input/output circuit for receiving and outputting a signal supplied through the fundamental programmable logic circuits and the programmable wiring means, at least said fundamental programmable logic circuits and said programmable wiring means being arranged in a matrix pattern.
Claim 2
Dependent Claim
226 words
A programmable logic circuit comprising: a data transfer circuit for outputting serial program data in a parallel manner; a plurality of fundamental programmable logic circuits each including first data storage sections arranged in a matrix pattern, said first data storage sections having signal output states which are programmed in accordance with parallel data supplied from the data transfer circuit, and a logic circuit pattern being programmed in accordance with at least outputs of the first data storage sections; a plurality of programmable wiring means, arranged in adjacent to the fundamental programmable logic circuits, for providing connection lines between the fundamental programmable logic circuits, said programmable wiring means including second data storage sections arranged in a matrix pattern, said second data storage sections having signal output states which are programmed in accordance with the parallel data supplied from the data transfer circuit, and switches located between the connection lines being selected or controlled in accordance with outputs of the second storage sections; a decoder circuit for causing the first and second storage sections to store data output from the data transfer circuit in response to address designation; and an input/output circuit for receiving and outputting a signal supplied through the fundamental programmable logic circuits and the programmable wiring means, at least said fundamental programmable logic circuits and said programmable wiring means being arranged in a matrix pattern.
Claim 3
Dependent Claim
54 words
A programmable logic circuit according to claim 1, wherein said programmable wiring means include first and second programmable wiring means selectively connected to each other by means of the switches and intersecting each other, and said second data storage sections are data storage sections additionally provided for the first and second programmable wiring means.
Claim 4
Dependent Claim
36 words
A programmable logic circuit according to claim 1, wherein said input/output circuit includes data storage sections which are arranged in a matrix pattern and which store data corresponding to an output of the data transfer circuit.
Claim 5
Dependent Claim
19 words
A programmable logic circuit according to claim 1, wherein said first and second data storage sections include flip-flop circuits.
Claim 6
Dependent Claim
21 words
A programmable logic circuit according to claim 1, wherein said decoder circuit has a disable terminal for disabling an output thereof.
Claim 7
Dependent Claim
23 words
A programmable logic circuit according to claim 1, wherein each of said switches is one of a one-direction switch and a bi-directional switch.
Claim 8
Dependent Claim
39 words
A programmable logic circuit according to claim 1, wherein the program data which is output by the data transfer circuit in a parallel manner is obtained from latch circuits used for latching parallel outputs of the data transfer circuit.
Claim 9
Dependent Claim
39 words
A programmable logic circuit according to claim 1, wherein said data transfer circuit, said fundamental programmable logic circuits, said programmable wiring means, said decoder circuit and said input/output circuit are fabricated as part of a large scale integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-25 | 1997-04-26 | 1997-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-25 | 2001-04-26 | 2001-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-25 | 2005-04-26 | 2005-10-26 | $7700.00 | Window Closed / Lapsed |