US4987319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable input/output circuit and programmable logic device
Assignee: Kawasaki Microelectronics Inc
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Filing: 1989-09-06
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Granted: 1991-01-22
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Expires: 2009-09-06
Abstract
Abstract In a programmable input/output circuit which is used in a programmable integrated circuit, for interfacing between an external circuit and an internal logic circuit, both disposed exteriorly and interiorly of said integrated circuit, an input/output terminal connected to a bus of the internal logic circuit and a tri-state input buffer are provided, and hereby assured that an external input signal is transmitted to either of the input/output terminal and an ordinary input terminal by switching the status of the tri-state input buffer. In a programmable logic device, which incorporates said input/output circuit, a tri-state buffer is provided between an input/output circuit block and a wiring element, and hereby a driving capability of the wiring element used as a bus line is increased.
Inventors
- 👤 Keiichi Kawana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/0175; H03K19/01759; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
114 words
A programmable input/output circuit for use in a programmable integrated circuit, for interfacing between an external circuit of the integrated circuit and an internal logic circuit of the same, the programmable input/output circuit comprising: (a) an input/output terminal connected to a bus of the internal logic circuit; (b) an input terminal connected to a programmable wiring of the internal logic circuit; (c) a tri-state input buffer means for transmitting an input signal fed externally of the circuit to any one of said input/output terminal and said input terminal, and (d) a tri-state output buffer means for transmitting externally of the circuit an output signal from the internal logic circuit fed to said input terminal.
Claim 2
Dependent Claim
114 words
A programmable input/output circuit for use in a programmable integrated circuit, for interfacing between an external circuit of the integrated circuit and an internal logic circuit of the same, the programmable input/output circuit comprising: (a) an input/output terminal connected to a bus of the internal logic circuit; (b) an input terminal connected to a programmable wiring of the internal logic circuit; (c) a tri-state input buffer means for transmitting an input signal fed externally of the circuit to any one of said input/output terminal and said input terminal, and (d) a tri-state output buffer means for transmitting externally of the circuit an output signal from the internal logic circuit fed to said input terminal.
Claim 3
Dependent Claim
42 words
A programmable input/output circuit according to claim 1 further comprising an input buffer which converts said input signal from a TTL or CMOS logical level to an internal logical level, said converted input signal being fed to said tri-state input buffer means.
Claim 4
Dependent Claim
60 words
A programmable input/output circuit according to claim 1 wherein said tri-state input buffer means includes a first tri-state input buffer which transmits said input signal to said input/output terminal and a second tri-state input buffer which is switched on and off in conformity with contents stored in a memory cell and which transmits said input signal to said input terminal.
Claim 5
Dependent Claim
50 words
A programmable input/output circuit according to claim 3 further comprising a two-input multiplexer including therein a memory cell, the multiplexer selecting any one of a chip enable signal and a logic low level signal entered through said input terminal as a status control signal for said first tri-state input buffer.
Claim 6
Dependent Claim
35 words
A programmable input/output circuit according to claim 1 wherein an on/off status of said output buffer means is controlled by an output enable signal applied from the internal logical circuit to an output control terminal.
Claim 7
Dependent Claim
52 words
A programmable input/output circuit according to claim 2 further comprising a pull-up resistor selectively connected to a pad through which said input signal is applied to said input buffer and a pass transistor including therein a memory cell, said pass transistor providing the selective connection between said pull-up resistor and said pad.
Claim 8
Dependent Claim
43 words
A programmable input/output circuit according to claim 2 further comprising a D flip-flop means for latching various signals from said input buffer and a two-input multiplexer means for selecting any one of an output from said D flip-flop means and an original signal.
Claim 9
Dependent Claim
61 words
A programmable input/output circuit according to claim 1, further comprising a first reset terminal for receiving a reset signal, a second reset terminal for receiving a global reset signal, and a NOR gate for outputting to said D flip-flop means as the reset signal the negation of a logicl sum of the signals applied to said first and second reset terminal.
Claim 10
Dependent Claim
83 words
A programmable logic device including a programmable input/output circuit block, comprising: (a) an input/output control terminal provided in said input/output circuit block; (b) wiring means capable of programming electrical connection, said wiring means being connected to a tri-state buffer; (c) said tri-state buffer being provided outside said input/output circuit block and including an enable control input terminal, said tri-state buffer being enable-controlled by a control signal; and (d) said input/output circuit block including an input control signal generator which generates said control signal.
Claim 11
Dependent Claim
83 words
A programmable logic device including a programmable input/output circuit block, comprising: (a) an input/output control terminal provided in said input/output circuit block; (b) wiring means capable of programming electrical connection, said wiring means being connected to a tri-state buffer; (c) said tri-state buffer being provided outside said input/output circuit block and including an enable control input terminal, said tri-state buffer being enable-controlled by a control signal; and (d) said input/output circuit block including an input control signal generator which generates said control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |