US4789951A
Expired / Lapsed
US
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Programmable array logic cell
Assignee: Lattice Semiconductor Corp
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Filing: 1986-05-16
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Granted: 1988-12-06
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Expires: 2006-05-16
Abstract
Abstract A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.
Inventors
- 👤 John M. Birkner
- 👤 Danesh M. Tavana
- 👤 Andrew K. Chan
- 👤 Sing Y. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:18
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
144 words
A programmable logic cell comprising: a plurality of logical AND gates, each gate having a plurality of input terminals and an output line; a plurality of cell input lines, selectively connectable to the input terminals of selected AND gates; a single logic OR gate having input terminals connected to selected AND gate output lines, and having an output line; a logical XOR gate having a first input terminal connected to the OR gate output line, having a second input terminal connected to an AND gate output line, and having an XOR output line on which the XOR gate provides a state signal; memory means to store the XOR output state signal; a cell output line coupled to the OR gate output line for providing a cell output signal; and feedback means selectively connectable to apply the state signal to selected AND gate input terminals.
Claim 2
Dependent Claim
144 words
A programmable logic cell comprising: a plurality of logical AND gates, each gate having a plurality of input terminals and an output line; a plurality of cell input lines, selectively connectable to the input terminals of selected AND gates; a single logic OR gate having input terminals connected to selected AND gate output lines, and having an output line; a logical XOR gate having a first input terminal connected to the OR gate output line, having a second input terminal connected to an AND gate output line, and having an XOR output line on which the XOR gate provides a state signal; memory means to store the XOR output state signal; a cell output line coupled to the OR gate output line for providing a cell output signal; and feedback means selectively connectable to apply the state signal to selected AND gate input terminals.
Claim 3
Dependent Claim
68 words
A cell as in claim 1 further characterized in that: said memory means is a D-type flip-flop circuit having a data signal input termnal and an enable signal input terminal, and responsive to an enable signal to sample a Qo' next state signal value from the flip-flop data input terminal, and to provide the sampled signal value Qo' as present state signal Qo at a meory output terminal.
Claim 4
Dependent Claim
41 words
A cell as in claim 2 wherein the feedback means includes an inverse output terminal in the flip-flop which provides the state signal inverse Qo, and includes phase splitter means which provide QQo and Qo on respective AND gate input terminals.
Claim 5
Dependent Claim
64 words
A cell as in claim 3 wherein the feedback means further includes a multiplexer having a first input terminal connected to the Qo output terminal of the flip-flop, a second input terminal connected to the cell output line, a control terminal connected through a programmable fuse to a reference potential, and an output terminal connected to provide signal Qo' to the phase splitter means.
Claim 6
Dependent Claim
56 words
A cell as in claim 3 further including a second multiplexer having a first input terminal connected to the flip-flop Qo output terminal, a second input terminal connected to the XOR gate output line, a control terminal connected through a programmable fuse to a reference potential, and an output terminal coupled to the cell output line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-06 | 1992-06-06 | 1992-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-06 | 1996-06-06 | 1996-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-06 | 2000-06-06 | 2000-12-06 | $7700.00 | Window Closed / Lapsed |