US4912345A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable summing functions for programmable logic devices
Assignee: STMicroelectronics lnc USA
•
Filing: 1988-12-29
•
Granted: 1990-03-27
•
Expires: 2008-12-29
Abstract
Abstract A programmable logic device includes a programmable logic array and an output logic macrocell. The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state.
Inventors
- 👤 Randy C. Steele
- 👤 Safoin A. Raad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
129 words
A programmable summing function for a programmable logic device comprising: a first logic gate connected to receive a first plurality of input signals; a second logic gate connected to receive a second plurality of input signals; a first NAND gate connected to receive the output of the first logic gate and a control signal; a second NAND gate connected to receive the output of the second logic gate and the control signal; and a logic circuit connected to receive outputs from the first and second logic gates and the first and second NAND gates, to provide an output signal for a first logical combination when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
Claim 2
Dependent Claim
129 words
A programmable summing function for a programmable logic device comprising: a first logic gate connected to receive a first plurality of input signals; a second logic gate connected to receive a second plurality of input signals; a first NAND gate connected to receive the output of the first logic gate and a control signal; a second NAND gate connected to receive the output of the second logic gate and the control signal; and a logic circuit connected to receive outputs from the first and second logic gates and the first and second NAND gates, to provide an output signal for a first logical combination when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
Claim 3
Dependent Claim
25 words
The programmable summing function for a programmable logic device according to claim 1 wherein the first and second logic gates each comprise an OR gate.
Claim 4
Dependent Claim
50 words
The programmable summing function for programmable logic devices according to claim 2 wherein the first logic state is a logic one and the first logical combination is an OR combination of a summation of the first plurality of input signals and a summation of the second plurality of input signals.
Claim 5
Dependent Claim
51 words
The programmable summing function for programmable logic devices according to claim 2 wherein the first logic state is a logic 0 and the first logical combination is an exclusive OR combination of a summation of the first plurality of input signals and a summation of the second plurality of input signals.
Claim 6
Dependent Claim
126 words
A programmable summing function for a programmable logic device comprising: a first NOR gate connected to receive a first plurality of input signals; a second NOR gate connected to receive a second plurality of input signals; a third NOR gate connected to receive the output of the first logic NOR gate and a control signal; a fourth NOR gate connected to receive the output of the second logic gate and the control signal; and a logic circuit connected to receive outputs from the first, second, third, and fourth NOR gates and to provide an output signal of a first logical combination when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
Claim 7
Dependent Claim
126 words
A programmable summing function for a programmable logic device comprising: a first NOR gate connected to receive a first plurality of input signals; a second NOR gate connected to receive a second plurality of input signals; a third NOR gate connected to receive the output of the first logic NOR gate and a control signal; a fourth NOR gate connected to receive the output of the second logic gate and the control signal; and a logic circuit connected to receive outputs from the first, second, third, and fourth NOR gates and to provide an output signal of a first logical combination when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
Claim 8
Dependent Claim
50 words
The programmable summing function for programmable logic devices according to claim 5 wherein the first logic state is logic 1 and the first logical combination is an exclusive OR combination of a summation of the first plurality of input signals and a summation of the second plurality of input signals.
Claim 9
Dependent Claim
129 words
A programmable summing function for a programmable logic device comprising; a first logic gate means for providing a first summation of a first plurality of input signals; a second logic gate means for providing a second summation of a second plurality of input signals; a first NAND gate for logically combining the first summation with a control signal and to provide a third summation; a second NAND gate for logically combining the second summation and the control signals and to provide a fourth summation; and a logic circuit means for combining in a first logic manner the first, second, third and fourth summation when the control signal is at a first logic state and in a second logic manner when the control signal is at a second logic state.
Claim 10
Dependent Claim
129 words
A programmable summing function for a programmable logic device comprising; a first logic gate means for providing a first summation of a first plurality of input signals; a second logic gate means for providing a second summation of a second plurality of input signals; a first NAND gate for logically combining the first summation with a control signal and to provide a third summation; a second NAND gate for logically combining the second summation and the control signals and to provide a fourth summation; and a logic circuit means for combining in a first logic manner the first, second, third and fourth summation when the control signal is at a first logic state and in a second logic manner when the control signal is at a second logic state.
Claim 11
Dependent Claim
28 words
The programmable summing function for programmable logic devices according to claim 7 wherein the first logic gate means and second logic gate means each comprise an OR gate.
Claim 12
Dependent Claim
21 words
The programmable summing function for programmable logic devices according to claim 7 wherein the first logical combination is an OR combination.
Claim 13
Dependent Claim
21 words
The programmable summing function for programmable logic devices according to claim 7 wherein the logical combination is an exclusive OR combination.
Claim 14
Dependent Claim
128 words
A programmable summing function for a programmable logic device comprising; a first logic gate means for providing a first summation of a first plurality of input signals; a second logic gate means for providing a second summation of a second plurality of input signals; a fist NOR gate for logically combining the first summation with a control signal and to provide a third summation; a second NOR gate for logically combining the second summation and the control signals and to provide a fourth summation; and a logic circuit means for combining in a first logic manner the first, second, third and fourth summation when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
Claim 15
Dependent Claim
128 words
A programmable summing function for a programmable logic device comprising; a first logic gate means for providing a first summation of a first plurality of input signals; a second logic gate means for providing a second summation of a second plurality of input signals; a fist NOR gate for logically combining the first summation with a control signal and to provide a third summation; a second NOR gate for logically combining the second summation and the control signals and to provide a fourth summation; and a logic circuit means for combining in a first logic manner the first, second, third and fourth summation when the control signal is at a first logic state and a second logical combination when the control signal is at a second logic state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |