US4609838A
Expired / Lapsed
US
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Programmable array combinatorial (PAC) circuitry
Assignee: Philips Semiconductors Inc
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Filing: 1984-05-30
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Granted: 1986-09-02
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Expires: 2004-05-30
Abstract
Abstract A plurality of product terms from an array of signals are combined by programmable array combinatorial (PAC) circuitry thereby permitting a variety of logic functions on the product terms. The PAC circuitry includes logic means for receiving first and second product terms and providing an output signal representing the first input, an OR function of the first and second inputs, or an exclusive OR function of the first and second inputs. The PAC circuitry can further include a shift register for providing a clock output signal. Inverter circuitry can be provided which responds to the control signals for inverting the output signal. The PAC circuitry is simple and readily implemented in a semiconductor integrated circuit thereby providing cost efficiency.
Inventors
- 👤 Eddy C. Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; H03K19/17704
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
100 words
Programmable array combinatorial circuitry comprising first and second gates for respectively receiving primary product terms and spare product terms and producing first and second signals representing said primary product terms and said spare product terms, first and second input terminals for receiving said first and second signals, respectively, and logic means operably connected to said first and second terminals for receiving said first and second signals and responsive to control signals for providing an output signal representing said first signal, an OR function of said first and second signals, or an exclusive OR function of said first and second signals.
Claim 2
Dependent Claim
100 words
Programmable array combinatorial circuitry comprising first and second gates for respectively receiving primary product terms and spare product terms and producing first and second signals representing said primary product terms and said spare product terms, first and second input terminals for receiving said first and second signals, respectively, and logic means operably connected to said first and second terminals for receiving said first and second signals and responsive to control signals for providing an output signal representing said first signal, an OR function of said first and second signals, or an exclusive OR function of said first and second signals.
Claim 3
Dependent Claim
16 words
The circuitry of claim 1 and further including register means connected to receive said output signal.
Claim 4
Dependent Claim
27 words
The circuitry as defined by claim 2 and further including inverter circuitry connected to said register means and responsive to control signals for inverting said output signal.
Claim 5
Dependent Claim
98 words
Programmable array combinatorial circuitry comprising first and second input terminals for receiving first and second signals representing primary product terms and spare product terms, respectively, logic means operably connected to said first and second terminals for receiving said first and second signals and responsive to control signals for providing an output signal representing said first input signal, an OR function of said first and second input signals, or an exclusive OR function of said first and second input signals, and inverter circuitry connected to receive said output signal and responsive to control signals for inverting said output signal.
Claim 6
Dependent Claim
98 words
Programmable array combinatorial circuitry comprising first and second input terminals for receiving first and second signals representing primary product terms and spare product terms, respectively, logic means operably connected to said first and second terminals for receiving said first and second signals and responsive to control signals for providing an output signal representing said first input signal, an OR function of said first and second input signals, or an exclusive OR function of said first and second input signals, and inverter circuitry connected to receive said output signal and responsive to control signals for inverting said output signal.
Claim 7
Dependent Claim
24 words
The circuitry as defined by claim 4 wherein said logic means includes a plurality of transmission gates controllably connected to receive said control signals.
Claim 8
Dependent Claim
52 words
The circuitry as defined by claim 5 wherein said control signals include an OR signal (POR) for said OR function, and exclusive OR signal (XOR) for said exclusive OR function, said output signal representing said first input signal in response to absence of both said OR signal and said exclusive OR signal.
Claim 9
Dependent Claim
39 words
The circuitry as defined by claim 4 and further including register means connected between said logic means and said inverter circuitry for receiving said output signal from said logic means and providing said output signal to said inverter circuitry.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |