Abstract A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device. In a still further form, the AND plane further includes a plurality of test input lines each associated with the corresponding one of the product term lines of the AND plane, and an three-state output buffer is connected between the OR plane and a device output terminal, whereby the output buffer is enabled by a logical sum between a selected product term from the AND plane and an internally supplied test mode signal.
A programmable logic device, comprising: a plurality of input terminals; an AND plane connected to said plurality of input terminals, said AND plane including a plurality of input lines extending in a predetermined direction, a plurality of product term lines extending in a direction transverse to said predetermined direction, and a plurality of programmable memory elements each disposed at each of cross-over points between said input and product term lines, said plurality of input lines being paired; an OR plane connected to said AND plane; at least one input-output terminal selectively connectable to at least one of said AND and OR planes; and wherein two pairs of said input lines are connected to at least one of said plurality of input terminals or to said input/output terminal and there are two independent feedback systems for selective feedback from said input/output terminal to said input lines; and wherein one of said paired input lines is an inverting input line and the remaining of said paired input lines is a non-inverting input line.
Claim 2
Dependent Claim
171 words
A programmable logic device, comprising: a plurality of input terminals; an AND plane connected to said plurality of input terminals, said AND plane including a plurality of input lines extending in a predetermined direction, a plurality of product term lines extending in a direction transverse to said predetermined direction, and a plurality of programmable memory elements each disposed at each of cross-over points between said input and product term lines, said plurality of input lines being paired; an OR plane connected to said AND plane; at least one input-output terminal selectively connectable to at least one of said AND and OR planes; and wherein two pairs of said input lines are connected to at least one of said plurality of input terminals or to said input/output terminal and there are two independent feedback systems for selective feedback from said input/output terminal to said input lines; and wherein one of said paired input lines is an inverting input line and the remaining of said paired input lines is a non-inverting input line.
Claim 3
Dependent Claim
38 words
The device of claim 1 further comprising a plurality of driver circuits each of which is connected to a corresponding one of said plurality of input terminals and is connected to said paired inverting and non-inverting input lines.