Multiple array customizable logic device

Claim 2

An integrated circuit having a plurality of input pins receiving input signals and a plurality of output pins, comprising: first programmable array means, coupled to the plurality of input pins, for receiving a plurality of first input terms and generating a plurality of first output terms including a first AND-array receiving the first input terms and generating first product terms, and a first OR-array receiving the first product terms and generating first sum-of-product terms for supply as the first output terms; second programmable array means, coupled to the plurality of output pins and to the first programmable array means, for receiving the plurality of first output terms and generating a plurality of second output terms for supply to the plurality of output pins including a second AND-array receiving the first output terms and generating second product terms and a second OR-array receiving the second product terms and generating second sum-of-product terms for supply as the second output terms.

Claim 3

An integrated circuit having a plurality of pins adapted for communicating signals to and from the circuit, comprising: first programmable array means, connected to receive a plurality of first input terms, for generating a plurality of first output terms; second programmable array means, connected to receive a plurality of second input terms, for generating a plurality of second output terms; input multiplexing means, responsive to an input select signal, for selecting and supplying a first subset of a set of input signals as the plurality of first input terms for the first programmable array means and a second subset of the set of input signals as the plurality of second input terms for the second programmable array means; means for supplying the input select signal; and input connecting means for connecting the set of input signals to the input multiplexing means, the set of input signals comprising a plurality of signals externally supplied to a first subset of the plurality of pins.

Claim 4

An integrated circuit having a plurality of pins adapted for communicating signals to and from the circuit, comprising: first programmable array means, connected to receive a plurality of first input terms, for generating a plurality of first output terms; second programmable array means, connected to receive a plurality of second input terms, for generating a plurality of second output terms; input multiplexing means, responsive to an input select signal, for selecting and supplying a first subset of a set of input signals as the plurality of first input terms for the first programmable array means and a second subset of the set of input signals as the plurality of second input terms for the second programmable array means; means for supplying the input select signal; and input connecting means for connecting the set of input signals to the input multiplexing means, the set of input signals comprising a plurality of signals externally supplied to a first subset of the plurality of pins.

Claim 5

The integrated circuit of claim 2, wherein: said first programmable array means includes at least one programmable array generating first logic terms; said second programmable array means includes at least one programmable array generating second logic terms; and said means for supplying said input select signal includes means connecting at least one logic term of said first and second logic terms as said input select signal.

Claim 6

The integrated circuit of claim 2, wherein said means for supplying said input select signal comprises: a fuse programmable signal generator.

Claim 7

The integrated circuit of claim 2, wherein: said first programmable array means includes an AND array connected to receive the first input terms generating first product terms and an OR array connected to receive the first product terms generating first sum-of-products terms for supply as the first output terms; said second programmable array means includes an AND array connected to receive the second input terms generating second product terms and an OR array connected to receive the second product terms generating second sum-of-product terms; wherein the first and second product terms and first and second sum-of-products terms are logic signals, and said means for supplying said input select signal supplies at least one of the logic signals as said input select signal.

Claim 8

The integrated circuit of claim 2, wherein the set of input signals further comprises a subset of the plurality of first output terms.

Claim 9

The integrated circuit of claim 6, wherein the set of input signals further comprises a subset of the plurality of second output terms.

Claim 10

The integrated circuit of claim 2, further including: a buried state means, connected to receive one output term of the plurality of first output terms, for storing the one output term and supplying a stored output term; and wherein the set of input signals further comprises the stored output term.

Claim 11

The integrated circuit of claim 2, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of logic signals, for storing the preselected plurality of logic signals and supplying a plurality of stored logic terms; and wherein the set of input signals further comprises the plurality of stored logic terms.

Claim 12

The integrated circuit of claim 2, further including: output multiplexing means, responsive to an output select signal, for selecting and supplying a subset of a set of output signals to a second subset of the plurality of pins; means for supplying the output select signal; and output connecting means for connecting the set of output signals to the output multiplexing means, the set of output signals comprising (1) a subset of the plurality of first output terms and (2) a subset of the plurality of second output terms.

Claim 13

The integrated circuit of claim 10, wherein: said first programmable array means includes at least one programmable array generating first logic terms; said second programmable array means includes at least one programmable array generating second logic terms; and said means for supplying said output select signal includes means connecting at least one logic term of said first and second logic terms as said output select signal.

Claim 14

The integrated circuit of claim 10, wherein said means for supplying said output select signal comprises: a fuse programmable signal generator.

Claim 15

The integrated circuit of claim 10, wherein: said first programmable array means includes an AND array connected to receive the first input terms generating first product terms and an OR array connected to receive the first product terms generating first sum-of-products terms for supply as the first output terms; said second programmable array means includes an AND array connected to receive the second input terms generating second product terms and an OR array connected to receive the second product terms generating second sum-of-product terms; wherein the first and second product terms and first and second sum-of-products terms are logic signals, and said means for supplying said output select signal supplies at least one of the logic signals as said output select signal.

Claim 16

The integrated circuit of claim 10, further including: a buried state means, connected to receive one output term of the plurality of first output terms, for storing the one output term and supplying a stored output term; and wherein the set of output signals further comprises the stored output term.

Claim 17

The integrated circuit of claim 10, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a plurality of stored logic terms; and wherein the set of output signals further comprises the plurality of stored logic terms.

Claim 18

The integrated circuit of claim 15 wherein said buried state means includes: a first set of registers of a first type for storing logic terms and a second set of registers of a second type for storing logic terms.

Claim 19

The integrated circuit of claim 10, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a plurality of stored logic terms; and wherein the set of input signals further comprises a first subset of the plurality of stored logic terms and the set of output signals further comprises a second subset of the plurality of stored logic terms.

Claim 20

An integrated circuit having a plurality of pins adapted for communicating signals to and from the circuit, comprising: first programmable array means, connected to receive a plurality of first input terms, for generating a plurality of first output terms; second programmable array means, connected to receive a plurality of second input terms, for generating a plurality of second output terms; first input multiplexing means, responsive to a first input select signal, for selecting and supplying a subset of a first set of input signals as the plurality of first input terms for the first programmable array means; second input multiplexing means, responsive to a second input select signal, for selecting and supplying a subset of a second set of input signals as the plurality of second input terms for the second programmable array means; means for supplying the first and second input select signals; input connecting means for connecting the first set of input signals to the first input multiplexing means and the second set of input signals to the second input multiplexing means, the first set of input signals comprising signals externally supplied to a first subset of the plurality of pins and the second set of input signals comprising signals externally supplied to a second subset of the plurality of pins; first output multiplexing means, responsive to a first output select signal, for selecting and supplying a subset of a first set of output signals to a third subset of the plurality of pins; second output multiplexing means, responsive to a second output select signal, for selecting and supplying a subset of a second set of output signals to a fourth subset of the plurality of pins; means for supplying the first and second output select signals; and output connecting means for connecting the first set of output signals to the first output multiplexing means and the second set of output signals to the second output multiplexing means, the first set of output signals comprising (1) a first subset of the plurality of first output terms and (2) a first subset of the plurality of second output terms and the second set of output signals comprising (1) a second subset of the plurality of second output terms.

Claim 21

An integrated circuit having a plurality of pins adapted for communicating signals to and from the circuit, comprising: first programmable array means, connected to receive a plurality of first input terms, for generating a plurality of first output terms; second programmable array means, connected to receive a plurality of second input terms, for generating a plurality of second output terms; first input multiplexing means, responsive to a first input select signal, for selecting and supplying a subset of a first set of input signals as the plurality of first input terms for the first programmable array means; second input multiplexing means, responsive to a second input select signal, for selecting and supplying a subset of a second set of input signals as the plurality of second input terms for the second programmable array means; means for supplying the first and second input select signals; input connecting means for connecting the first set of input signals to the first input multiplexing means and the second set of input signals to the second input multiplexing means, the first set of input signals comprising signals externally supplied to a first subset of the plurality of pins and the second set of input signals comprising signals externally supplied to a second subset of the plurality of pins; first output multiplexing means, responsive to a first output select signal, for selecting and supplying a subset of a first set of output signals to a third subset of the plurality of pins; second output multiplexing means, responsive to a second output select signal, for selecting and supplying a subset of a second set of output signals to a fourth subset of the plurality of pins; means for supplying the first and second output select signals; and output connecting means for connecting the first set of output signals to the first output multiplexing means and the second set of output signals to the second output multiplexing means, the first set of output signals comprising (1) a first subset of the plurality of first output terms and (2) a first subset of the plurality of second output terms and the second set of output signals comprising (1) a second subset of the plurality of second output terms.

Claim 22

The integrated circuit of claim 18, wherein: at least a subset of said signals externally supplied to the first subset of the plurality of pins include clock signals, and at least a subset of said plurality of first input terms and said plurality of second input terms include the clock signals.

Claim 23

The integrated circuit of claim 18 wherein: said first programmable array means includes a fuse programmable logic array generating sum-of-products terms; and said second programmable array means includes a fuse programmable logic array generating sum-of-products terms.

Claim 24

The integrated circuit of claim 18, wherein: said first programmable array means includes an AND array connected to receive the first input terms generating first product terms and an OR array connected to receive the first product terms generating first sum-of-products terms for supply as the first output terms; said second programmable array means includes an AND array connected to receive the second input terms generating second product terms and an OR array connected to receive the second product terms generating second sum-of-product terms; wherein the first and second product terms and first and second sum-of-products terms are logic signals, and said means for supplying said input select signal supplies at least one of the logic signals as said input select signal.

Claim 25

The integrated circuit of claim 18 wherein means for supplying said input select signal comprises: a fuse programmable signal generator.

Claim 26

The integrated circuit of claim 18 wherein said means for supplying said output select signal comprises: a fuse programmable signal generator.

Claim 27

The integrated circuit of claim 18, wherein the second set of output signals further comprises a second subset of the plurality of first output terms.

Claim 28

The integrated circuit of claim 18, wherein the second set of input signals further comprises a second subset of the plurality of first output terms.

Claim 29

The integrated circuit of claim 18, wherein the first set of input signals further comprises a second subset of the plurality of first output terms.

Claim 30

The integrated circuit of claim 18, wherein the second set of input signals further comprises a third subset of the plurality of second output terms.

Claim 31

The integrated circuit of claim 18, wherein the first set of input signals further comprises a third subset of the plurality of second output terms.

Claim 32

The integrated circuit of claim 18, wherein the first set of input signals further comprises a third subset of the plurality of second output terms and a second subset of the plurality of first output terms.

Claim 33

The integrated circuit of claim 18, wherein the second set of input signals further comprises a third subset of the plurality of second output terms and a second subset of the plurality of first output terms.

Claim 34

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein the first set of input signals further comprises a subset of the set of stored logic terms.

Claim 35

The integrated circuit of claim 31 wherein said buried state means includes: a first set of registers of a first type for storing logic terms and a second set of registers of a second type for storing logic terms.

Claim 36

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein: the second set of input signals further comprises a subset of the set of stored logic terms.

Claim 37

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein: the first set of input signals further comprises a first subset of the set of stored logic terms and the second set of input signals further comprises a second subset of the set of stored logic terms.

Claim 38

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein: the first set of output signals further comprises a subset of the set of stored logic terms.

Claim 39

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and further including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein: the second set of output signals further comprises a subset of the set of stored logic terms.

Claim 40

The integrated circuit of claim 18, wherein the first output terms and the second output terms are logic signals, and furhter including: buried state means, connected to receive a preselected plurality of the logic signals, for storing the preselected plurality of logic signals and supplying a set of stored logic terms; and wherein the first set of output signals further comprises a first subset of the set of stored logic terms and the second set of output signals further comprises a second subset of the set of stored logic terms.