RAM/ROM hybrid memory architecture

Claim 2

An integrated circuit memory, comprising: an array of memory cells arranged in rows and columns, with word lines running along rows of said array; word line driver circuitry, connected to drive a selected one of said word lines when one of said cells in said selected row is sought to be accessed; a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage; wherein each said cell in said array includes: a latch having first and second nodes, two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit line pair; and wherein at least some of said cells in said array each also include: nonvolatile shorting elements, connected to pull one of said nodes of said latch toward a constant potential.

Claim 3

The integrated circuit of claim 1, wherein said nonvolatile shorting elements comprise laser-programmable fuses.

Claim 4

The integrated circuit of claim 1, wherein said nonvolatile shorting elements comprise a pair of fuse elements, which are respectively in series with a pair of switching transistors.

Claim 5

The integrated circuit of claim 1, wherein said nonvolatile shorting elements comprise a pair of fuse elements, which are respectively in series with a pair of switching transistors, and multiple ones of said switching transistors are commonly controlled by a signal derived from a further nonvolatile storage element.

Claim 6

The integrated circuit of claim 1, further comprising a respective pair of switching transistors which are respectively in series with ones of said pairs of shorting elements in said cells.

Claim 7

The integrated circuit of claim 1, further comprising a respective pair of switching transistors which are respectively in series with ones of said pairs of shorting elements in said cells, wherein multiple ones of said switching transistors are commonly controlled by a signal derived from a further nonvolatile storage element.

Claim 8

The integrated circuit of claim 1, wherein said nonvolatile shorting elements comprise EPROM transistors.

Claim 9

The integrated circuit of claim 1, wherein some ones of said cells include said nonvolatile shorting elements, and other ones of said cells do not include said nonvolatile shorting elements.

Claim 10

The integrated circuit of claim 1, wherein, in every one of said columns, either all ones of said cells include said nonvolatile shorting elements, or else all ones of said cells do not include said nonvolatile shorting elements.

Claim 11

The integrated circuit of claim 1, wherein said word line driver circuitry and said sense amplification and output stage are configured to operate on a power supply voltage of less than 2 Volts, and which is less than the sum of NMOS and PMOS threshold voltages.

Claim 12

An integrated circuit memory, comprising: an array of memory cells arranged in rows and columns, with word lines running along rows of said array; word line driver circuitry, connected to drive a selected one of said word -- lines when one of said cells in said selected row is sought to be accessed; a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage; wherein each said cell in said array includes: a latch having first and second nodes, two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit -- line pair; and wherein at least some of said cells in said array each also include: a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a first substantially constant potential, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and a second substantially constant potential.

Claim 13

An integrated circuit memory, comprising: an array of memory cells arranged in rows and columns, with word lines running along rows of said array; word line driver circuitry, connected to drive a selected one of said word -- lines when one of said cells in said selected row is sought to be accessed; a sense amplification and output stage, connected to amplify the output of a selected one of said cells, and column selection circuitry, configured to connect the output of a selected one of said cells to said sense amplification and output stage; wherein each said cell in said array includes: a latch having first and second nodes, two pass transistors, controlled by a respective one of said word lines, and operable to connect said first and second nodes of said latch to a respective bit -- line pair; and wherein at least some of said cells in said array each also include: a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a first substantially constant potential, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and a second substantially constant potential.

Claim 14

The integrated circuit of claim 11, wherein said fuse elements consist essentially of laser-programmable fuses.

Claim 15

The integrated circuit of claim 11, wherein multiple ones of said switching transistors, in multiple ones of said cells, are commonly controlled by a signal derived from a further nonvolatile storage element.

Claim 16

The integrated circuit of claim 11, wherein some ones of said cells include said fuse elements, and other ones of said cells do not include said fuse elements.

Claim 17

The integrated circuit of claim 11, wherein, in each respective one of said columns, either all ones of said cells include said fuse elements, or else all ones of said cells do not include said fuse elements.

Claim 18

The integrated circuit of claim 11, wherein said circuit is a CMOS circuit including NMOS and PMOS devices and wherein said word line driver circuitry and said sense amplification and output stage are configured to operate on a power supply voltage which is less than 2 volts and also less than the sum of an NMOS device threshold voltage plus a PMOS device threshold voltage.

Claim 19

An integrated circuit memory cell, comprising: a latch having first and second nodes, comprising a first NMOS driver transistor, having a source connected to pull down said first node, and a gate connected to said second node; a second NMOS driver transistor, having a source connected to pull down said second node, and a gate connected to said first node; first and second load elements, connected to pull up said first and second nodes respectively; two pass transistors, operable to connect said first and second nodes, repectively, to a bit -- line pair; a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a ground, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and said ground.

Claim 20

An integrated circuit memory cell, comprising: a latch having first and second nodes, comprising a first NMOS driver transistor, having a source connected to pull down said first node, and a gate connected to said second node; a second NMOS driver transistor, having a source connected to pull down said second node, and a gate connected to said first node; first and second load elements, connected to pull up said first and second nodes respectively; two pass transistors, operable to connect said first and second nodes, repectively, to a bit -- line pair; a first fuse element, and a first switching transistor in series with said first fuse element, connected between said first node of said latch and a ground, and a second fuse element, and a second switching transistor in series with said second fuse element, connected between said second node of said latch and said ground.

Claim 21

The cell of claim 17, wherein said load elements consist essentially of PMOS transistors.

Claim 22

The cell of claim 17, wherein said pass transistors are NMOS transistors.

Claim 23

The cell of claim 17, wherein said pass transistors are NMOS transistors, and have approximately the same gate width to length ratios as said switching transistors.