US4855803A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selectively definable semiconductor device
Assignee: Ricoh Co Ltd
•
Filing: 1988-07-26
•
Granted: 1989-08-08
•
Expires: 2008-07-26
Abstract
Abstract A selectively definable semiconductor device is provided. In one form, a composite gate array includes a plurality of logic dedicated general purpose cell regions and a plurality of function dedicated cell regions each of which is disposed between the two corresponding ones of the plurality of logic dedicated general purpose cell regions, whereby each of the cell regions may be used as an interconnection region selectively. In another form, a semiconductor memory device which may be selectively defined as a ROM or a RAM by a metalization process is provided.
Inventors
- 👤 Hideo Azumai
- 👤 Koichi Fujii
- 👤 Takashi Seigenji
- 👤 Keiichi Yoshioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:31
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A composite gate-array semiconductor device, comprising: a plurality of logic dedicated general purpose cell regions, each capable of providing a desired logic function and also capable of providing an interconnection function selectively; a plurality of function dedicated cell regions, each capable of providing a desired function and also capable of providing an interconnection function selectively, each of said plurality of function dedicated cell regions being disposed between two corresponding ones of said plurality of logic dedicated general purpose cell regions; a pair of adjacent bit lines; wherein said plurality of function dedicated cell regions include a plurality of RAM/ROM cells which can be selectively defined either as RAM cells or as ROM cells by metallization and which are connected to said adjacent bit lines; and a one-bit decoder which is connected between said pair of adjacent bit lines when said plurality of RAM/ROM cells are defined as ROM cells.
Claim 2
Dependent Claim
149 words
A composite gate-array semiconductor device, comprising: a plurality of logic dedicated general purpose cell regions, each capable of providing a desired logic function and also capable of providing an interconnection function selectively; a plurality of function dedicated cell regions, each capable of providing a desired function and also capable of providing an interconnection function selectively, each of said plurality of function dedicated cell regions being disposed between two corresponding ones of said plurality of logic dedicated general purpose cell regions; a pair of adjacent bit lines; wherein said plurality of function dedicated cell regions include a plurality of RAM/ROM cells which can be selectively defined either as RAM cells or as ROM cells by metallization and which are connected to said adjacent bit lines; and a one-bit decoder which is connected between said pair of adjacent bit lines when said plurality of RAM/ROM cells are defined as ROM cells.
Claim 3
Dependent Claim
22 words
The device of claim 1 wherein said regions, each elongated in shape, are arranged in a row spaced apart from each other.
Claim 4
Dependent Claim
53 words
The device of claim 1 wherein at least some of said plurality of logic dedicated general purpose cell regions are interconnected by some of said plurality of function dedicated cell regions to define a desired random logic function, whereby said some of said plurality of function dedicated cell regions serve as interconnection regions.
Claim 5
Dependent Claim
31 words
The device of claim 1 wherein at least one of said plurality of function dedicated cell regions has a function as a memory, D/A converter, operational amplifier or arithmetic logic unit.
Claim 6
Dependent Claim
75 words
The device of claim 1 wherein said plurality of function dedicated cell regions include a plurality of RAM cells arranged in a plurality of rows; a plurality of first X decoders each provided for each row of said plurality of RAM cells; a Y decoder operatively associated with each of said plurality of RAM cells; a sense circuit operatively associated with said Y decoder; and a R/W control circuit operatively associated with said sense circuit.
Claim 7
Dependent Claim
31 words
The device of claim 5 wherein said plurality of logic dedicated general purpose cell regions include a second X decoder operatively associated with each of said plurality of first X decoders.
Claim 8
Dependent Claim
33 words
The device of claim 6 wherein said plurality of logic dedicated general purpose cell regions further include an address buffer which is operatively associated with said second X decoder and said Y decoder.
References Cited (Backward Citations)
US101804A
Cited
US3798621A
Cited
US4005393A
Cited
US3969706A
Cited
US4161662A
Cited
US4103185A
Cited
US4072932A
Cited
UST101804I4
Cited
JPS5727109A
Cited
JPS5911670A
Cited
US4553053A
Cited
JPS60105251A
Cited
US4623911A
Cited
US4584669A
Cited
JPH0650695A
Cited
JPH0664447A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-07 | 1993-02-06 | 1993-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-07 | 1997-02-06 | 1997-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-07 | 2001-02-06 | 2001-08-08 | $7700.00 | Window Closed / Lapsed |