US4072932A
Expired / Lapsed
US
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Clock generator for semiconductor memory
Assignee: Texas Instruments Inc
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Filing: 1976-08-23
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Granted: 1978-02-07
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Expires: 1996-08-23
Abstract
Abstract Disclosed is a read clock generator for use in a semiconductor memory. The read clock generator is comprised of a bistable amplifier and a differential voltage sensor. The bistable amplifier is activated during a read cycle; and it simulates the transient operation of a plurality of sense amplifiers which sense binary information stored within the memory. The differential voltage sensor couples to the bistable amplifier, and produces an output signal when the bistable amplifier stabilizes.
Inventors
- 👤 Norihisa Kitagawa
- 👤 Lionel S. White, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/408; G11C11/4091
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
118 words
A semiconductor memory comprised of: a. an array of memory cell means for storing binary information, b. a plurality of sense amplifier means coupled to said array of memory cell means for reading selectable portions of said memory information in response to control signals, and c. read-clock generator means for generating output signals indicating when said plurality of sense amplifier means has stabilized during said reading wherein said generator means includes timing circuit means having inputs coupled to receive said control signals and having substantially the same architecture as said sense amplifier means for simulating during said reading the transient operation of said sense amplifiers and for generating said output signals indicating when said timing circuit is stable.
Claim 2
Dependent Claim
118 words
A semiconductor memory comprised of: a. an array of memory cell means for storing binary information, b. a plurality of sense amplifier means coupled to said array of memory cell means for reading selectable portions of said memory information in response to control signals, and c. read-clock generator means for generating output signals indicating when said plurality of sense amplifier means has stabilized during said reading wherein said generator means includes timing circuit means having inputs coupled to receive said control signals and having substantially the same architecture as said sense amplifier means for simulating during said reading the transient operation of said sense amplifiers and for generating said output signals indicating when said timing circuit is stable.
Claim 3
Dependent Claim
22 words
A semiconductor memory according to claim 1, wherein said timing means and said sense amplifier means are comprised of intercoupled MOS transistors.
Claim 4
Dependent Claim
24 words
A semiconductor memory according to claim 2, wherein said timing means and said sense amplifier means are comprised of bi-stable cross-coupled MOS amplifier means.
Claim 5
Dependent Claim
40 words
A semiconductor memory according to claim 3, wherein each of said bi-stable amplifier means is comprised of a set transistor cross-coupled to a reset transistor, said cross-coupling forming set and reset nodes, said nodes within said timing means being unbalanced.
Claim 6
Dependent Claim
53 words
A semiconductor memory according to claim 4, further including a differential voltage sensing means coupled to said set and reset nodes within said timing means for generating said output signal in response to the voltage on said set node being more than one MOS threshold different than the voltage on said reset node.
Claim 7
Dependent Claim
36 words
A semiconductor memory according to claim 5, wherein said differential voltage sensing means is comprised of an MOS transistor having a gate coupled to said reset node and having a drain coupled to said set node.
Claim 8
Dependent Claim
116 words
In a semiconductor binary memory comprised of arrays of cells for storing binary information and a plurality of sense amplifier means coupled to said cells for reading selectable cells in response to control signals, an improved read-clock generator means for producing clock signals indicating when said sense amplifiers having stabilized during said reading comprised of: a. bi-stable amplifier means having inputs coupled to receive said control signals and having substantially the same architecture as said sense amplifiers for simulating during said read cycle the transient operation of said sense amplifiers, and b. differential voltage sensor means coupled to said bi-stable amplifier means for producing said clock signal in response to said bi-stable amplifier means becoming stable.
Claim 9
Dependent Claim
116 words
In a semiconductor binary memory comprised of arrays of cells for storing binary information and a plurality of sense amplifier means coupled to said cells for reading selectable cells in response to control signals, an improved read-clock generator means for producing clock signals indicating when said sense amplifiers having stabilized during said reading comprised of: a. bi-stable amplifier means having inputs coupled to receive said control signals and having substantially the same architecture as said sense amplifiers for simulating during said read cycle the transient operation of said sense amplifiers, and b. differential voltage sensor means coupled to said bi-stable amplifier means for producing said clock signal in response to said bi-stable amplifier means becoming stable.
Claim 10
Dependent Claim
26 words
Read-clock generator means according to claim 7, wherein said sense amplifiers, said bi-stable amplifier means, and said voltage sensor means are comprised of intercoupled MOS transistors.
Claim 11
Dependent Claim
30 words
Read-clock generator means according to claim 8, wherein said bi-stable amplifier means is comprised of a set transistor cross-coupled to a reset transistor to form unbalanced set and reset nodes.
Claim 12
Dependent Claim
34 words
Read-clock generator means according to claim 9, wherein said differential voltage sensing means is comprised of a transistor having a gate coupled to said reset node and a drain coupled to said set node.
Claim 13
Dependent Claim
43 words
Read-clock generator means according to claim 8, wherein said bi-stable amplifier means is comprised of a set transistor cross-coupled to a reset transistor to form set and reset nodes, said set and reset nodes being coupled to a pair of unbalanced load transistors.
Claim 14
Dependent Claim
34 words
Read-clock generator means according to claim 11, wherein said differential voltage sensing means is comprised of a transistor having a gate coupled to said reset node and a drain coupled to said set node.
References Cited (Backward Citations)
US3855483A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |