US4005393A
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US
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Bipolar semiconductor memory with recharging circuit for capacitively loaded lines
Assignee: Wincor Nixdorf International GmbH
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Filing: 1975-06-04
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Granted: 1977-01-25
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Expires: 1995-06-04
Abstract
Abstract A bipolar semiconductor memory has a matrix of word-by-word selectable memory cells and selective circuits associated therewith in the word direction and in the bit direction for selective memory words in response to receipt of address signals. A decoder includes output switches in the form of emitter followers which are connected to respective word lines. The memory cells present capacitive loads to the lines and a recharging circuit is connected to each word line of the matrix and includes a common constant current source which is connected to each word line by way of a respective coupling element. Each of the coupling elements are embodied as base-emitter paths of recharge transistors which have the respective collectors connected directly to a respective word line. A base resistance is also connected between the respective word line and the bae of a recharge transistor.
Inventors
- 👤 Reinhard Schuerba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:58
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
156 words
A bipolar semiconductor memory system comprising: a word organized memory including a plurality of memory cells arranged in a matrix of columns and rows, a plurality of bit lines each connected to each memory cell of a respective column, and a plurality of word lines each connected to each memory cell of a respective row, said memory cells constituting a capacitive load connected to said lines; a decoder for receiving address signals for selecting memory words, said decoder including a plurality of emitter follower output switches each connected to a respective word line; and a recharging circuit connected to each word line of said memory, said recharging circuit including a common constant current generator for said word lines, and a plurality of coupling circuits each connecting a respective word line to said constant current generator, each of said coupling circuits comprising a diode structure connected between a respective word line and said common constant current generator.
Claim 2
Dependent Claim
156 words
A bipolar semiconductor memory system comprising: a word organized memory including a plurality of memory cells arranged in a matrix of columns and rows, a plurality of bit lines each connected to each memory cell of a respective column, and a plurality of word lines each connected to each memory cell of a respective row, said memory cells constituting a capacitive load connected to said lines; a decoder for receiving address signals for selecting memory words, said decoder including a plurality of emitter follower output switches each connected to a respective word line; and a recharging circuit connected to each word line of said memory, said recharging circuit including a common constant current generator for said word lines, and a plurality of coupling circuits each connecting a respective word line to said constant current generator, each of said coupling circuits comprising a diode structure connected between a respective word line and said common constant current generator.
Claim 3
Dependent Claim
180 words
A bipolar semiconductor memory system comprising: a word organized memory including a plurality of memory cells arranged in a matrix of columns and rows, a plurality of bit lines each connected to each memory cell of a respective column, and a plurality of word lines each connected to each memory cell of a respective row, said memory cells constituting a capacitive load connected to said lines; a decoder for receiving address signals for selecting memory words, said decoder including a plurality of emitter follower output switches each connected to a respective word line; and a recharging circuit connected to each word line of said memory, said recharging circuit including a common constant current generator for said word lines, and a plurality of coupling circuits each connecting a respective word line to said constant current generator, each of said coupling circuits comprising a transistor including a base, an emitter and a collector, said emitter connected to said common constant current generator and said collector connected to the respective word line, and a resistor connecting said base to the respective word line.
Claim 4
Dependent Claim
180 words
A bipolar semiconductor memory system comprising: a word organized memory including a plurality of memory cells arranged in a matrix of columns and rows, a plurality of bit lines each connected to each memory cell of a respective column, and a plurality of word lines each connected to each memory cell of a respective row, said memory cells constituting a capacitive load connected to said lines; a decoder for receiving address signals for selecting memory words, said decoder including a plurality of emitter follower output switches each connected to a respective word line; and a recharging circuit connected to each word line of said memory, said recharging circuit including a common constant current generator for said word lines, and a plurality of coupling circuits each connecting a respective word line to said constant current generator, each of said coupling circuits comprising a transistor including a base, an emitter and a collector, said emitter connected to said common constant current generator and said collector connected to the respective word line, and a resistor connecting said base to the respective word line.
References Cited (Backward Citations)
US3546682A
Cited
US3786442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-25 | 1980-07-26 | 1981-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-25 | 1984-07-26 | 1985-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-25 | 1988-07-26 | 1989-01-25 | $7700.00 | Window Closed / Lapsed |