Series linear antifuse array

Claim 2

In a user-programmable interconnect architecture wherein potential connections may be made between a first interconnect conductor and a plurality of second interconnect conductors, interconnection apparatus including: an isolation conductor; a plurality of connection antifuses, a different one of said connection antifuses connected between said isolation conductor and each one of said plurality of second interconnect conductors; a single isolation antifuse connected between said first interconnect conductor and said isolation conductor, said single isolation antifuse and said isolation conductor acting to limit parasitic capacitance of said first interconnect conductor to a value less than the capacitance of said isolation antifuse; and programming means for programming said isolation antifuse.

Claim 3

The interconnection apparatus of claim 1 further including an isolation transistor connected between said first interconnect conductor and said isolation conductor.

Claim 4

The interconnection apparatus of claim 1 wherein said programming means comprises: a transistor connected between said isolation conductor and a circuit node which may be held at a first voltage potential; and circuit means for connecting a second voltage potential to said first interconnect conductor, the difference between said first and second voltage potentials being sufficient to program said isolation antifuse.

Claim 5

The interconnection apparatus of claim 3 wherein said transistor is a pull-down transistor.

Claim 6

A programmable interconnect architecture comprising: a first interconnect conductor; a plurality of second interconnect conductors; forming intersections with said first conductor; a plurality of antifuses, individual ones of said antifuses disposed at said intersections; an isolation conductor; a single isolation antifuse connected between said first interconnect conductor and said isolation conductor, said single isolation antifuse and said isolation conductor acting to limit parasitic capacitance of said first interconnect conductor to a value less than the capacitance of said isolation antifuse; and programming means for programming said isolation antifuse.

Claim 7

A programmable interconnect architecture comprising: a first interconnect conductor; a plurality of second interconnect conductors; forming intersections with said first conductor; a plurality of antifuses, individual ones of said antifuses disposed at said intersections; an isolation conductor; a single isolation antifuse connected between said first interconnect conductor and said isolation conductor, said single isolation antifuse and said isolation conductor acting to limit parasitic capacitance of said first interconnect conductor to a value less than the capacitance of said isolation antifuse; and programming means for programming said isolation antifuse.

Claim 8

The programmable interconnect architecture of claim 5 further including an isolation transistor connected between said first interconnect conductor and said isolation conductor.

Claim 9

The programmable interconnect architecture of claim 5 wherein said programming means comprises: a transistor connected between said isolation conductor and a circuit node which may be held at a first voltage potential; and circuit means for connecting a second voltage potential to said first interconnect conductor, the difference between said first and second voltage potentials being sufficient to program said isolation antifuse.

Claim 10

The programmable interconnect architecture of claim 7 wherein said transistor is a pull-down transistor.

Claim 11

In a user-programmable interconnect architecture wherein potential connections may be made between a first interconnect conductor and a plurality of second interconnect conductors, said architecture further including interconnection apparatus comprising an isolation conductor, a single isolation antifuse connected between said first interconnect conductor and said isolation conductor, a plurality of connection antifuses, a different one of said connection antifuses connected between said isolation conductor and each one of said plurality of second interconnect conductors, and programming means for programming said isolation antifuse, wherein said isolation antifuse and said isolation conductor act to limit parasitic capacitance of said first interconnect conductor to a value less than the capacitance of said isolation antifuse, a method for forming a connection between said first interconnect conductor and a selected one of said second interconnect conductors, including the steps of: programming said isolation antifuse; and placing a programming voltage potential across said isolation conductor and said selected one of said second conductors.

Claim 12

In a user-programmable interconnect architecture wherein potential connections may be made between a first interconnect conductor and a plurality of second interconnect conductors, said architecture further including interconnection apparatus comprising an isolation conductor, a single isolation antifuse connected between said first interconnect conductor and said isolation conductor, a plurality of connection antifuses, a different one of said connection antifuses connected between said isolation conductor and each one of said plurality of second interconnect conductors, and programming means for programming said isolation antifuse, wherein said isolation antifuse and said isolation conductor act to limit parasitic capacitance of said first interconnect conductor to a value less than the capacitance of said isolation antifuse, a method for forming a connection between said first interconnect conductor and a selected one of said second interconnect conductors, including the steps of: programming said isolation antifuse; and placing a programming voltage potential across said isolation conductor and said selected one of said second conductors.

Claim 13

A user-programmable interconnect architecture comprising: a plurality of first conductors running in a first direction; a plurality of second conductors running in said first direction, each of said second conductors associated with a different one of said first conductors; a plurality of third conductors running in a second direction not parallel to said first direction; a plurality of fourth conductors running in said second direction, each of said second conductors associated with a different one of said third conductors, said fourth conductors forming intersections with said second conductors; a plurality of connection antifuses, a different one of said antifuses connected between intersecting ones of said second and fourth conductors; a first isolation transistor connected between each said first conductor and its associated second conductor; a single first isolation antifuse connected between each said first conductor and its associated second conductor, said single first isolation antifuse and said second conductor acting to limit parasitic capacitance of said first conductor to a value less than the capacitance of said isolation antifuse; a second isolation transistor connected between each said third conductor and its associated fourth conductor; a single second isolation antifuse connected between each said third conductor and its associated fourth conductor, said single second isolation antifuse and said fourth conductor acting to limit parasitic capacitance of said third conductor to a value less than the capacitance of said isolation antifuse; means for selectively connecting each of said second and fourth conductors to a first voltage potential; and circuit means for selectively connecting a second voltage potential to ones of said first and third conductors, the difference between said first and second voltage potentials being sufficient to program said first and second isolation antifuses.

Claim 14

A user-programmable interconnect architecture comprising: a plurality of first conductors running in a first direction; a plurality of second conductors running in said first direction, each of said second conductors associated with a different one of said first conductors; a plurality of third conductors running in a second direction not parallel to said first direction; a plurality of fourth conductors running in said second direction, each of said second conductors associated with a different one of said third conductors, said fourth conductors forming intersections with said second conductors; a plurality of connection antifuses, a different one of said antifuses connected between intersecting ones of said second and fourth conductors; a first isolation transistor connected between each said first conductor and its associated second conductor; a single first isolation antifuse connected between each said first conductor and its associated second conductor, said single first isolation antifuse and said second conductor acting to limit parasitic capacitance of said first conductor to a value less than the capacitance of said isolation antifuse; a second isolation transistor connected between each said third conductor and its associated fourth conductor; a single second isolation antifuse connected between each said third conductor and its associated fourth conductor, said single second isolation antifuse and said fourth conductor acting to limit parasitic capacitance of said third conductor to a value less than the capacitance of said isolation antifuse; means for selectively connecting each of said second and fourth conductors to a first voltage potential; and circuit means for selectively connecting a second voltage potential to ones of said first and third conductors, the difference between said first and second voltage potentials being sufficient to program said first and second isolation antifuses.