US5338961A
Expired / Lapsed
US
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High power MOSFET with low on-resistance and high breakdown voltage
Assignee: Infineon Technologies Americas Corp
•
Filing: 1993-02-12
•
Granted: 1994-08-16
•
Expires: 2013-02-12
Abstract
Abstract A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.
Inventors
- 👤 Alexander Lidow
- 👤 Thomas Herman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/663; H10D30/662; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
409 words
A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth; said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means; said gate electrode means overlying said first and second channel regions; a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region; said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced; said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.
Claim 2
Dependent Claim
409 words
A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth; said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means; said gate electrode means overlying said first and second channel regions; a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region; said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced; said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.
Claim 3
Dependent Claim
22 words
The high power metal oxide silicon field effect transistor device of claim 1 wherein said device is formed by DMOS manufacturing techniques.
Claim 4
Dependent Claim
40 words
The high power metal oxide silicon field effect transistor device of claim 1; said at least first and second spaced base regions being diffused regions and being diffused from said first and second first surface locations to said common regions.
Claim 5
Dependent Claim
15 words
The device of claim 1 wherein said drain electrode is on said second semiconductor surface.
Claim 6
Dependent Claim
14 words
The device of claim 1 wherein said drain electrode is on said first surface.
Claim 7
Dependent Claim
23 words
The device of claim 5 wherein said drain conductive region is a high conductivity diffused region and is disposed beneath said drain electrode.
Claim 8
Dependent Claim
15 words
The device of claim 6 which further includes electrode means fixed to said second surface.
Claim 9
Dependent Claim
29 words
The device of claim 5 wherein a buried conductive region contacts a region of said opposite conductivity type which extends from said buried conductive region to said second surface.
Claim 10
Dependent Claim
33 words
The device of claim 8 wherein there is at least one additional highly doped isolation region of said opposite conductivity type extending into said wafer from said first surface and surrounding said device.
Claim 11
Dependent Claim
42 words
The device of claim 5 further comprising a generally annular, low-resistivity region of said opposite conductivity type surrounding said drain electrode; said generally annular region extending deep enough into said wafer to isolate said device electrically from other components on said wafer.
Claim 12
Dependent Claim
19 words
The device of claim 5, wherein said one conductivity type is N-type and said opposite conductivity type is P-type.
Claim 13
Dependent Claim
21 words
The device of claim 1 wherein said relatively lightly doped major body portion of said wafer is an epitaxially formed layer.
Claim 14
Dependent Claim
27 words
the device of claim 12 wherein said epitaxial layer has a thickness of about 20 microns and is dependent upon the desired reverse voltage of the device.
Claim 15
Dependent Claim
14 words
The device of claim 1 wherein said gate insulation layer means is silicon dioxide.
Claim 16
Dependent Claim
24 words
The device of claim 1 wherein said first and second channel regions and said gate electrode means are elongated along a closed serpentine path.
Claim 17
Dependent Claim
18 words
The device of claim 1 wherein said first and second channel regions are elongated around closed parallel paths.
Claim 18
Dependent Claim
17 words
The device of claim 16 wherein one of said first and second source regions surrounds the other.
Claim 19
Dependent Claim
22 words
The device of claim 1 wherein said one conductivity type is the n-type and wherein said opposite conductive type is the p-type.
Claim 20
Dependent Claim
84 words
The device of claim 1 wherein each of said at least first and second spaced base regions of said opposite conductivity type have respective profiles which includes relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region.
Claim 21
Dependent Claim
17 words
The device of claim 19 wherein said relatively deep regions have a depth of about 4 microns.
Claim 22
Dependent Claim
23 words
The device of claim 1 wherein said depth to which said common region is relatively highly doped is greater than about 1 micron.
Claim 23
Dependent Claim
22 words
The device of claim 1 wherein said depth to which said common region is highly doped is about 3 to 6 microns.
Claim 24
Dependent Claim
14 words
The device of claim 1 wherein said gate electrode means is formed of polysilicon.
Claim 25
Dependent Claim
21 words
The device of claim 1 wherein said relatively lightly doped body portion has a resistivity greater than about 2.5 ohm centimeters.
Claim 26
Dependent Claim
47 words
The device of claim 1 wherein said relatively highly doped common region is doped to a conductivity which is of the order of magnitude which would be produced by a total ion implanted dose of about 1×10 12 to 1×10 14 phosphorus atoms/cm 2 at 50 kv.
Claim 27
Dependent Claim
424 words
A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth; said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said first surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means; said gate electrode means overlying said first and second channel regions; a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region; said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region but less than said first depth of said first and second spaced base regions, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced; said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.
Claim 28
Dependent Claim
424 words
A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage; said device comprising: a wafer of semiconductor material having first and second opposing semiconductor surfaces; said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type; at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface; the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location; first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth; said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region; source electrode means connected to said source regions; gate insulation layer means on said first surface, disposed at least on said first and second channel regions; gate electrode means on said gate insulation layer means; said gate electrode means overlying said first and second channel regions; a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion; a drain electrode coupled to said drain conductive region; said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region but less than said first depth of said first and second spaced base regions, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced; said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.
Claim 29
Dependent Claim
22 words
The high power metal oxide silicon field effect transistor device of claim 26 wherein said device is formed by D-MOS manufacturing techniques.
Claim 30
Dependent Claim
40 words
The high power metal oxide silicon field effect transistor device of claim 26; said at least first and second spaced base regions being diffused regions and being diffused from said first and second first surface locations to said common region.
Claim 31
Dependent Claim
15 words
The device of claim 26 wherein said drain electrode is on said second semiconductor surface.
Claim 32
Dependent Claim
14 words
The device of claim 26 wherein said drain electrode is on said first surface.
Claim 33
Dependent Claim
23 words
The device of claim 30 wherein said drain conductive region is a high conductivity diffused region and is disposed beneath said drain electrode.
Claim 34
Dependent Claim
15 words
The device of claim 31 which further includes electrode means fixed to said second surface.
Claim 35
Dependent Claim
29 words
The device of claim 30 wherein a buried conductive region contacts a region of said opposite conductivity type which extends from said buried conductive region to said second surface.
Claim 36
Dependent Claim
33 words
The device of claim 33 wherein there is at least one additional highly doped isolation region of said opposite conductivity type extending into said wafer from said first surface and surrounding said device.
Claim 37
Dependent Claim
42 words
The device of claim 30, further comprising a generally annular, low-resistivity region of said opposite conductivity type surrounding said drain electrode; said generally annular region extending deep enough into said wafer to isolate said device electrically from other components on said wafer.
Claim 38
Dependent Claim
19 words
The device of claim 30, wherein said one conductivity type is N-type and said opposite conductivity type is P-type.
Claim 39
Dependent Claim
21 words
The device of claim 26 wherein said relatively lightly doped major body portion of said wafer is an epitaxially formed layer.
Claim 40
Dependent Claim
27 words
The device of claim 37 wherein said epitaxial layer has a thickness of about 20 microns and is dependent upon the desired reverse voltage of the device.
Claim 41
Dependent Claim
14 words
The device of claim 26 wherein said gate insulation layer means is silicon dioxide.
Claim 42
Dependent Claim
24 words
The device of claim 26 wherein said first and second channel regions and said gate electrode means are elongated along a closed serpentine path.
Claim 43
Dependent Claim
18 words
The device of claim 26 wherein said first and second channel regions are elongated around closed parallel paths.
Claim 44
Dependent Claim
17 words
The device of claim 41 wherein one of said first and second source regions surrounds the other.
Claim 45
Dependent Claim
22 words
The device of claim 26 wherein said one conductivity type is the n-type and wherein said opposite conductivity type is the p-type.
Claim 46
Dependent Claim
84 words
The device of claim 26 wherein each of said at least first and second spaced base regions of said opposite conductivity type have respective profiles which include relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region.
Claim 47
Dependent Claim
17 words
The device of claim 44 wherein said relatively deep regions have a depth of about 4 microns.
Claim 48
Dependent Claim
23 words
The device of claim 26 wherein said depth to which said common region is relatively highly doped is greater than about 1 micron.
Claim 49
Dependent Claim
22 words
The device of claim 26 wherein said depth to which said common region is highly doped is about 3 to 6 microns.
Claim 50
Dependent Claim
14 words
The device of claim 26 wherein said gate electrode means is formed of polysilicon.
Claim 51
Dependent Claim
21 words
The device of claim 26 wherein said relatively lightly doped body portion has a resistivity greater than about 2.5 ohm centimeters.
Claim 52
Dependent Claim
47 words
The device of claim 26 wherein said relatively highly doped common region is doped to a conductivity which is of the order of magnitude which would be produced by a total ion implanted dose of about 1×10 12 to 1×10 14 phosphorus atoms/cm 2 at 50 kv.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |