US4680853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide
Assignee: Infineon Technologies Americas Corp
•
Filing: 1986-05-30
•
Granted: 1987-07-21
•
Expires: 2006-05-30
Abstract
Abstract A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.
Inventors
- 👤 Alexander Lidow
- 👤 Thomas Herman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D30/662; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D30/665; H10D62/17; H10D62/393; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/926
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
225 words
A process for fabricating a power semiconductor device, comprising the steps of: (a) providing a wafer having first and second layers, said first layer being of one conductivity type and having a greater resistivity than said second layer; (b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer; (c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region; (d) forming respective shallow base regions laterally aaround the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions; (e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions; (f) providing a gate electrode atop said dielectric layer; and (g) contacting said source regions with electrically conductive materal to form a source electrode.
Claim 2
Dependent Claim
225 words
A process for fabricating a power semiconductor device, comprising the steps of: (a) providing a wafer having first and second layers, said first layer being of one conductivity type and having a greater resistivity than said second layer; (b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer; (c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region; (d) forming respective shallow base regions laterally aaround the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions; (e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions; (f) providing a gate electrode atop said dielectric layer; and (g) contacting said source regions with electrically conductive materal to form a source electrode.
Claim 3
Dependent Claim
29 words
The process of claim 1, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant of said opposite conductivity type into said first layer.
Claim 4
Dependent Claim
35 words
The process of claim 2, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant in a dosage range of 5×10 13 to 1×10 15 dopant atoms per square centimeter.
Claim 5
Dependent Claim
28 words
The process of claim 1, wherein said introduction of dopant to form said common region comprises implanation of dopant of said one conductivity type into said first layer.
Claim 6
Dependent Claim
34 words
The process of claim 4, wherein said introduction of dopant to form said common region comprises implantation of dopant in a dosage range from 1×10 11 to 1×10 14 dopant atoms per square centimeter.
Claim 7
Dependent Claim
21 words
The process of claim 1, wherein said one conductivity type comprises N-conductivity type, and said opposite conductivity type comprises P-conductivity type.
Claim 8
Dependent Claim
237 words
A process for fabricating a power MOSFET, comprising the steps of: (a) providing a wafer of one conductivity type having first and second layers, said first layer being of low conductivity relative to said second layer; (b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer; (c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region; (d) forming respective shallow base regions laterally around the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions; (e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions; (f) providing a gate electrode atop said dielectric layer; (g) contacting said source regions with electrically conductive material to form a source electrode; and (h) contacting said second layer with electrically conductive material to form a drain electrode.
Claim 9
Dependent Claim
237 words
A process for fabricating a power MOSFET, comprising the steps of: (a) providing a wafer of one conductivity type having first and second layers, said first layer being of low conductivity relative to said second layer; (b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer; (c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region; (d) forming respective shallow base regions laterally around the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions; (e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions; (f) providing a gate electrode atop said dielectric layer; (g) contacting said source regions with electrically conductive material to form a source electrode; and (h) contacting said second layer with electrically conductive material to form a drain electrode.
Claim 10
Dependent Claim
29 words
The process of claim 7, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant of said opposite conductivity type into said first layer.
Claim 11
Dependent Claim
35 words
The process of claim 8, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant in a dosage range of 5×10 13 to 1×10 15 dopant atoms per square centimeter.
Claim 12
Dependent Claim
28 words
The process of claim 7, wherein said introduction of dopant to form said common region comprises implantation of dopant of said one conductivity type into said first layer.
Claim 13
Dependent Claim
34 words
The process of claim 10, wherein said introduction of dopant to form said common region comprises implantation of dopant in a dosage range from 1×10 11 to 1×10 14 dopant atoms per square centimeter.
Claim 14
Dependent Claim
21 words
The process of claim 7, wherein said one conductivity type comprises N-conductivity type, and said opposite conductivity type comprises P-conductivity type.
References Cited (Backward Citations)
US4015278A
Cited
US4072975A
Cited
US4055884A
Cited
JPS5374385A
Cited
JPS54885A
Cited
US4148047A
Cited
US4593302A
Cited
US4593302B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-20 | 1991-01-19 | 1991-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-20 | 1995-01-19 | 1995-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-20 | 1999-01-19 | 1999-07-21 | $7700.00 | Window Closed / Lapsed |