US3749985A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High frequency insulated gate field effect transistor for wide frequency band operation
Assignee: RCA Corp
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Filing: 1972-04-10
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Granted: 1973-07-31
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Expires: 1992-04-10
Abstract
Abstract An insulated gate field effect transistor adapted for use at high frequencies, with usable gain within a broad range of frequencies, includes a plurality of dual gate MOS transistor unit structures, each with good characteristics for high frequency operation, interconnected in parallel on a single semiconductor body. The parallel combination provides a relatively high ratio of transconductance to output load capacitance and the gain bandwidth product of the device is therefore relatively high. The unit structures are formed in a substrate region including a ground plane. The means for interconnecting the unit structures in parallel includes a diffused region for connecting one gate electrode of each unit to the corresponding gate electrode of the others. This diffused region lies close to each unit structure to provide a local capacitive high frequency by-pass to ground. Low capacitance beam leads for connecting the device to external circuitry further reduce output loading capacitances.
Inventors
- 👤 R Dawson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:26
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D30/611; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/254; H10W; H10W20/00; H10W20/20; H10D62/00; H10D62/10; H10D62/124; H10D62/126
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
167 words
An insulated gate field effect transistor adapted for operation at high frequencies comprising a substrate of semiconductive material of one type conductivity, means in and on said substrate for defining A plurality of dual insulated gate field effect transistor unit structures, each unit structure comprising a source region, a first channel region, an intermediate source-drain region, a second channel region, a drain region, a first insulated gate adjacent to said first channel region, and a second insulated gate adjacent to said second channel region, and means interconnecting the respective source regions, drain regions and first and second gates of said unit structures in parallel, said means including at least one diffused conductor region of conductivity type opposite to that of said substrate, in said substrate and defining a PN junction therewith, said diffused conductor region extending from a location near the periphery of said substrate to points closely adjacent to each unit structure, the second gates of each unit structure being connected to said diffused conductor region.
Claim 2
Dependent Claim
167 words
An insulated gate field effect transistor adapted for operation at high frequencies comprising a substrate of semiconductive material of one type conductivity, means in and on said substrate for defining A plurality of dual insulated gate field effect transistor unit structures, each unit structure comprising a source region, a first channel region, an intermediate source-drain region, a second channel region, a drain region, a first insulated gate adjacent to said first channel region, and a second insulated gate adjacent to said second channel region, and means interconnecting the respective source regions, drain regions and first and second gates of said unit structures in parallel, said means including at least one diffused conductor region of conductivity type opposite to that of said substrate, in said substrate and defining a PN junction therewith, said diffused conductor region extending from a location near the periphery of said substrate to points closely adjacent to each unit structure, the second gates of each unit structure being connected to said diffused conductor region.
Claim 3
Dependent Claim
165 words
An insulated gate field effect transistor as defined in claim 1 wherein said substrate comprises a body of semiconductive material of said one type conductivity but of relatively high degree of conductivity and an epitaxial layer of said one type conductivity but of relatively lower degree of conductivity on said body, said PN junction being within said layer, said epitaxial layer having a coating of insulating material thereon, said coating having openings at predetermined locations therein to enable contact to be made to said epitaxial layer, and wherein said interconnecting means further includes conductive means connecting each source region to said body of semiconductive material, at least one deposited conductor on said insulating coating interconnecting the first gates of each unit structure and extending to a location at the periphery of said substrate, and at least one other deposited conductor on said insulating coating extending through openings therein to interconnect said drain regions and also extending to a location at the periphery of said substrate.
Claim 4
Dependent Claim
55 words
An insulated gate field effect transistor as defined in claim 2 wherein said conductive means connecting the sources to the body comprises a diffused region of said one type conductivity adjacent to each unit structure and extending through said epitaxial layer to said body, and means ohmically connecting each source region to said diffused region.
Claim 5
Dependent Claim
24 words
An insulated gate field effect transistor as defined in claim 2 wherein substantially all of said drain connecting conductor overlies said diffused conductor region.
Claim 6
Dependent Claim
50 words
An insulated gate field effect transistor as defined in claim 4 wherein said PN junction defined by said diffused conductor region has a predetermined area whereby it exhibits a predetermined range of capacitances determined by the voltages applied to said second gates when said transistor is operated in a circuit.
Claim 7
Dependent Claim
41 words
An insulated gate field effect transistor as defined in claim 2 wherein at least a portion of said diffused conductor region has the configuration of an elongated strip, the unit structures adjacent to said strip lying symetrically on opposite sides thereof.
Claim 8
Dependent Claim
59 words
An insulated gate field effect transistor as defined in claim 6 wherein said drain connecting conductor has an elongated portion extending in generally parallel relation to and lying centrally over said portion of said diffused conductor region, said drain connecting conductor further having portions extending normally to said elongated portion thereof to terminations in contact with said drain regions.
Claim 9
Dependent Claim
70 words
An insulated gate field effect transistor as defined in claim 1 further comprising an electrode connected to said body for coupling said source regions to external circuitry, and cantilevered beam leads at the periphery of said substrate, one connected to each of said first gate connecting and drain connecting conductors and said diffused conductor region for connecting said first gates, said drains, and said second gates, respectively, to external circuitry.
Claim 10
Dependent Claim
74 words
An insulated gate field effect transistor as defined in claim 8 wherein there are a plurality of said first gate connecting conductors each terminating at the periphery of said substrate, the beam lead connected thereto having a plurality of cantilevered portions, one portion contacting each of said plurality of first gate connecting conductors, and having a joining portion interconnecting said cantilevered portions, said joining portion being spaced away from the periphery of said substrate.
Claim 11
Dependent Claim
72 words
An insulated gate field effect transistor as defined in claim 9 wherein there are a plurality of said drain connecting conductors each terminating at the periphery of said substrate, the beam lead connected thereto having a plurality of cantilevered portions, one portion contacting each of said plurality of drain connecting conductors, and having a joining portion interconnecting said cantilevered portions, said joining portion being spaced away from the periphery of said substrate.
References Cited (Backward Citations)
US3073428A
Cited
US3465293A
Cited
US3541543A
Cited
US3653978A
Cited
US3590342A
Cited
US3575609A
Cited
US3652906A
Cited
US3657614A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |