Two-phase ultra-fast micropower dynamic shift register

Claim 2

Data storage circuit apparatus comprising: first, second and third terminal means for respectively receiving first, second and third discrete input signals; first signal storage means; first switching means responsive to said first input signal and operative to couple said second terminal means to said first signal storage means; second signal storage means; second switching means having a first pair of control inputs for receiving respectively, a signal stored in said first signal storage means and said first input signal, said second switching means being operative to couple said first terminal means to said second storage means in response to a signal applied to either of said first pair of control inputs; third signal storage means; third switching means responsive to said third input signal and operative to couple signals stored in said second signal storage means into said third signal storage means; fourth signal storage means; fourth switching means having a second pair of control inputs for receiving a signal stored in said third signal storage means and said third input signal, said fourth switching means being operative to couple said third terminal means to said fourth storage means in response to a signal applied to either of said second pair of control inputs; and output terminal means coupled to said fourth signal storage means.

Claim 3

Data storage circuit apparatus as recited in claim 1 wherein said switching means are field-effect transistor means.

Claim 4

Data storage circuit apparatus as recited in claim 2 wherein said first and third switching means are respectively comprised of a single field-effect transistor means and said second and fourth switching means are respectively comprised of two field-effect transistor means connected in parallel.

Claim 5

Data storage circuit apparatus as recited in claim 3 wherein said circuit apparatus is an integrated circuit means formed on a single chip of semiconductive material.

Claim 6

Data storage circuit apparatus as recited in claim 4 wherein said signal storage means are comprised of certain inherent PN junction capacitances of the respective integrated circuit components.

Claim 7

Data storage circuit apparatus as recited in claim 5 wherein said first and third input signals are clock phase signals which are respectively 90* out of phase with each other, and said second input signal is a digital input signal whereby said data storage circuit apparatus acts as a high-speed two clock phase dynamic shift register cell.

Claim 8

An integrated circuit shift register apparatus comprised of an array of a plurality of shift register cells as recited in claim 6, all of said cells being disposed on a single chip of semiconductive material.

Claim 9

Integrated circuit shift register apparatus for causing an input signal to be delayed by a predetermined interval of time comprising: a first clock phase interconnect Means and a second clock phase interconnect means; input terminal means and output terminal means; first FET means having a first gate, a first source and a first drain, said first gate being coupled to said first interconnect means and said first source being coupled to said input terminal means; second FET means having a second gate, a second source and a second drain, said second gate being coupled to said first drain and said second source being coupled to said first interconnect means; third FET means having a third gate, a third source and a third drain, said third gate being coupled to said first interconnect means, said third source being coupled to said second source, and said third drain being coupled to said second drain; fourth FET means having a fourth gate, a fourth source and a fourth drain, said fourth gate being coupled to said second interconnect means and said fourth source being coupled to said second drain and said third drain; fifth FET means having a fifth gate, a fifth source and a fifth drain, said fifth gate being coupled to said fourth drain, said fifth source being coupled to said second interconnect means, and said fifth drain being coupled to said output terminal means; and sixth FET means having a sixth gate, a sixth source and a sixth drain, said sixth gate and said sixth source being coupled to said second interconnect means and said sixth drain being coupled to said output terminal means.

Claim 10

Integrated circuit shift register apparatus for causing an input signal to be delayed by a predetermined interval of time comprising: a first clock phase interconnect Means and a second clock phase interconnect means; input terminal means and output terminal means; first FET means having a first gate, a first source and a first drain, said first gate being coupled to said first interconnect means and said first source being coupled to said input terminal means; second FET means having a second gate, a second source and a second drain, said second gate being coupled to said first drain and said second source being coupled to said first interconnect means; third FET means having a third gate, a third source and a third drain, said third gate being coupled to said first interconnect means, said third source being coupled to said second source, and said third drain being coupled to said second drain; fourth FET means having a fourth gate, a fourth source and a fourth drain, said fourth gate being coupled to said second interconnect means and said fourth source being coupled to said second drain and said third drain; fifth FET means having a fifth gate, a fifth source and a fifth drain, said fifth gate being coupled to said fourth drain, said fifth source being coupled to said second interconnect means, and said fifth drain being coupled to said output terminal means; and sixth FET means having a sixth gate, a sixth source and a sixth drain, said sixth gate and said sixth source being coupled to said second interconnect means and said sixth drain being coupled to said output terminal means.

Claim 11

An integrated circuit shift register apparatus as recited in claim 8 wherein the source and drain regions of said FET means are of p-type impurity diffused into an n-type semiconductive substrate.

Claim 12

An integrated circuit shift register apparatus as recited in claim 9 wherein said FET means are formed in a single semiconductive wafer and said interconnect means are comprised of metallic strips arrayed parallel to each other over a surface of said wafer and respectively include tablike projections which extend over predetermined portions of the drain regions of said second and third FET means, and said fifth and sixth FET means respectively, so as to increase the gate-to-source capacitance of said first and fourth FET means.