Field effect transistor with a short channel length

Claim 2

A field effect transistor with a MIS gate arrangement and with a source and drain regions in a semiconductor body, an electrically conductive zone additionally provided which lies in said semiconductor body beneath the source zone and which is of a conductivity type opposite to a portion of the semiconductor body surrounding it, wherein in the region of the controllable field effect by said gate arrangement (2) said additional zone (9) is spaced a distance (a) from said gate arrangement and from the boundary surface between the semiconductor body (1) and the gate insulation layer (2), and is bounded by an edge which forms a channel having a width "c" in said zone (9) and which projects laterally by a distance (b) beyond the edge of the source zone (4) into the path of charge carriers and where the distance (b) is approximately 1 to 10 times the thickness (d) of the gate insulation layer (2), and the distance (a) is approximately 1 to 5 times the thickness (d) of the gate insulation layer (2) and where the ratio of b:a is approximately equal to 1:1 to 10:1, the source zone (4) and the zone (9) are of opposite conductivity types and the degree of doping of the zone (9) is selected to be such that with the maximum provided electrical operating voltage between the drain electrode (6) and the source zone (4), the majority charge carriers of the zone (9) are not depleted.

Claim 3

A field effect transistor as claimed in claim 1, wherein said source region (4,) and said conductive zone (9,) are formed as rotation-symmetrical arrangements and said zone (9,) lies between said drain region (6) and said source region (4,).

Claim 4

A field effect transistor as claimed in claim 1, wherein said source region is formed as two strips (4, 14) electrically connected together and with said gate arrangement (2,) between said two strips (4, 14).

Claim 5

A field effect transistor as claimed in claim 1, wherein said source region (4) and said drain region (62) are formed in the same surface of said semiconductor body (61).

Claim 6

A field effect transistor as claimed in claim 1, wherein the area of said source region (71) is less than the area of said gate arrangement (2,) and the area of said zone (79) is greater than the area of said source region (71) and less than the area of said gate arrangement (2,) and said source region (71) lies between the gate arrangement (2,) and the zone (79).

Claim 7

A field effect transistor with a MIS gate arrangement and with a source and drain regions in a semiconductor body, an electrically conductive zone additional provided which lies in said semiconductor body beneath the source zone and which has an electrical conductivity higher than a portion of a semiconductor body surrounding it, wherein in the region of te controllable field effect by said gate arrangement (2) said additional zone (9) is spaced a distance (a) from said gate arrangement and from the boundary surface between the semiconductor body (1) and the gate insulation layer (2), and is bounded by an edge which forms a channel having a width "c" in said zone (9) and which projects laterally by a distance (b) beyond the edge of the source zone (4) into the path of charge carriers and where the distance (b) is approximately 1 to 10 times the thickness (d) of the gate insulation layer (2), and the distance (a) is approximately 1 to 5 times the thickness (d) of the gate insulation layer (2) and where the ration of b:a is approximately equal to 1:1 to 10:1, the source zone (4) and the zone (9) are of opposite conductivity types and the degree of doping of the zone (9) is selected to be such that with the maximum provided electrical operating voltage between the drain electrode (6) and the source zone (4), the majority charge carriers of the zone (9) are not depleted.

Claim 8

A field effect transistor with a MIS gate arrangement and with a source and drain regions in a semiconductor body, an electrically conductive zone additional provided which lies in said semiconductor body beneath the source zone and which has an electrical conductivity higher than a portion of a semiconductor body surrounding it, wherein in the region of te controllable field effect by said gate arrangement (2) said additional zone (9) is spaced a distance (a) from said gate arrangement and from the boundary surface between the semiconductor body (1) and the gate insulation layer (2), and is bounded by an edge which forms a channel having a width "c" in said zone (9) and which projects laterally by a distance (b) beyond the edge of the source zone (4) into the path of charge carriers and where the distance (b) is approximately 1 to 10 times the thickness (d) of the gate insulation layer (2), and the distance (a) is approximately 1 to 5 times the thickness (d) of the gate insulation layer (2) and where the ration of b:a is approximately equal to 1:1 to 10:1, the source zone (4) and the zone (9) are of opposite conductivity types and the degree of doping of the zone (9) is selected to be such that with the maximum provided electrical operating voltage between the drain electrode (6) and the source zone (4), the majority charge carriers of the zone (9) are not depleted.

Claim 9

A field effect transistor as claimed in claim 6, wherein said source region (4) and said conductive zone (9) are formed as rotation-symmetrical arrangements and said zone (9) lies between said drain region (6) and said source region (4).

Claim 10

A field effect transistor as claimed in claim 6 wherein said source region is formed as two strips (4, 14) electrically connected together and with said gate arrangement (2) between said two strips (4, 14).

Claim 11

A field effect transistor as claimed in claim 6 wherein said source region (4) and said drain region (62) are formed in the same surface of said semiconductor body (61).

Claim 12

A field effect transistor as claimed in claim 6 wherein the area of said source region (71) is less than the area of said gate arrangement (2) and the area of said zone (79) is greater than the area of said source region (71) and less than the area of said gate arrangement (2) and said source region (71) lies between the gate arrangement (2) and the zone (79).