US4007478A — Field effect transistor

Claim 1

Independent Claim 294 words

An MIS field effect transistor comprising: a body of semiconductor material including a. a first region of semiconductor material of one conductivity type extending to a surface of said body; b. a second region of semiconductor material of the same type conductivity as that of said first region and extending to said surface and being spaced laterally from said first region; c. a single substantially cup-shaped region only of semiconductor material of the opposite type conductivity to that of said first and second regions, said cup-shaped region containing said second region and having a portion located between said first and second regions and forming at least one PN junction therewith, said portion of the cup-shaped region of semiconductor material extending to said surface of the semiconductor body to provide a narrow channel; and d. a buried region of semiconductor material of the opposite conductivity type having a greater impurity concentration than that of said cup-shaped region and being at least substantially laterally coextensive with, and located in underlying relation to said cup-shaped region and in contact therewith over substantially the entire lateral extent of the latter, said buried region being spaced laterally from said first region with the margin of said buried region which is closest to said first region being spaced from said first region in the lateral direction toward said cup-shaped region; e. first and second electrodes respectively connected to said first and second regions at said surface; f. a control electrode electrically insulated from the semiconductor body and being positioned substantially over the entire area of said portion of said cup-shaped region extending to the surface of said body; and g. means to apply a potential to said cup-shaped region through said buried region from the outside of said semiconductor body.

Claim 2

Dependent Claim 294 words

An MIS field effect transistor comprising: a body of semiconductor material including a. a first region of semiconductor material of one conductivity type extending to a surface of said body; b. a second region of semiconductor material of the same type conductivity as that of said first region and extending to said surface and being spaced laterally from said first region; c. a single substantially cup-shaped region only of semiconductor material of the opposite type conductivity to that of said first and second regions, said cup-shaped region containing said second region and having a portion located between said first and second regions and forming at least one PN junction therewith, said portion of the cup-shaped region of semiconductor material extending to said surface of the semiconductor body to provide a narrow channel; and d. a buried region of semiconductor material of the opposite conductivity type having a greater impurity concentration than that of said cup-shaped region and being at least substantially laterally coextensive with, and located in underlying relation to said cup-shaped region and in contact therewith over substantially the entire lateral extent of the latter, said buried region being spaced laterally from said first region with the margin of said buried region which is closest to said first region being spaced from said first region in the lateral direction toward said cup-shaped region; e. first and second electrodes respectively connected to said first and second regions at said surface; f. a control electrode electrically insulated from the semiconductor body and being positioned substantially over the entire area of said portion of said cup-shaped region extending to the surface of said body; and g. means to apply a potential to said cup-shaped region through said buried region from the outside of said semiconductor body.

Claim 3

Dependent Claim 232 words

An insulated-gate field effect transistor comprising: a. a semiconductor substrate, a first region of diffused semiconductor material of one conductivity type in said substrate; b. a second region of diffused semiconductor material of the opposite conductivity type in said substrate to provide a source region, said second diffused region being within said first diffused region so that said first region forms a shell-like narrow channel region having an edge portion extending to the semiconductor surface; c. a drain region of the opposite conductivity type in said semiconductor substrate and spaced laterally from said first region; d. a region buried in said substrate and being of semiconductor material of the same type conductivity as that of said first region but having a greater impurity concentration than that of said first region, said buried region being at least substantially laterally coextensive with, and located in underlying relation to said first region and in contact therewith over substantially the entire lateral extent of the latter, the margin of said buried region which is closest to said drain region being spaced from said drain region in the lateral direction toward said first region; e. a first electrode connected to said drain region; f. a second electrode connected to said second region as a source electrode; and g. a control electrode electrically insulated from the semiconductor surface and positioned over said edge portion of said channel region.

Claim 4

Dependent Claim 232 words

An insulated-gate field effect transistor comprising: a. a semiconductor substrate, a first region of diffused semiconductor material of one conductivity type in said substrate; b. a second region of diffused semiconductor material of the opposite conductivity type in said substrate to provide a source region, said second diffused region being within said first diffused region so that said first region forms a shell-like narrow channel region having an edge portion extending to the semiconductor surface; c. a drain region of the opposite conductivity type in said semiconductor substrate and spaced laterally from said first region; d. a region buried in said substrate and being of semiconductor material of the same type conductivity as that of said first region but having a greater impurity concentration than that of said first region, said buried region being at least substantially laterally coextensive with, and located in underlying relation to said first region and in contact therewith over substantially the entire lateral extent of the latter, the margin of said buried region which is closest to said drain region being spaced from said drain region in the lateral direction toward said first region; e. a first electrode connected to said drain region; f. a second electrode connected to said second region as a source electrode; and g. a control electrode electrically insulated from the semiconductor surface and positioned over said edge portion of said channel region.

Claim 5

Dependent Claim 38 words

An insulated-gate field effect transistor as claimed in claim 2; in which the impurity concentration of a region of said substrate extending under said drain region from said buried region is lower than that of said channel region.

Claim 6

Dependent Claim 82 words

An insulated-gate field effect transistor as claimed in claim 2, in which an additional buried layer is formed in underlying relation to said drain region, the conductivity type of said additional buried layer being the same as that of the first mentioned buried region but the impurity concentration of said additional buried layer being lower than that of said first mentioned buried region, and said additional buried layer extending contiguous to said first mentioned buried region at an end of the latter.

Claim 7

Dependent Claim 233 words

An insulated-gate field effect transistor comprising: a. a semiconductor substrate; b. first and second diffused regions of a first conductivity type laterally spaced in said semiconductor substrate and extending to a surface of the latter; c. third and fourth diffused regions of a second conductivity type, said third diffused region being wholly within said first region and said fourth diffused region extending from within said second region beyond the latter at one end of said second region toward said first region; d. a drain region of the second conductivity type in said semiconductor substrate and spaced laterally from said second region at the other end of the latter; e. a buried region which is of the same conductivity type as that of said first and second regions but has an impurity concentration higher than the latter, said buried region being spaced from said drain region and located in underlying relation to said first and second regions and in contact therewith over substantially the entire lateral extents of said first and second regions; f. an electrode for said drain region; g. a source electrode for said third region; h. a first control electrode which is electrically insulated from said surface of the semiconductor at an end of said first region; and i. a second control electrode which is electrically insulated from said surface of the semiconductor at said other end of said second region.

Claim 8

Dependent Claim 233 words

An insulated-gate field effect transistor comprising: a. a semiconductor substrate; b. first and second diffused regions of a first conductivity type laterally spaced in said semiconductor substrate and extending to a surface of the latter; c. third and fourth diffused regions of a second conductivity type, said third diffused region being wholly within said first region and said fourth diffused region extending from within said second region beyond the latter at one end of said second region toward said first region; d. a drain region of the second conductivity type in said semiconductor substrate and spaced laterally from said second region at the other end of the latter; e. a buried region which is of the same conductivity type as that of said first and second regions but has an impurity concentration higher than the latter, said buried region being spaced from said drain region and located in underlying relation to said first and second regions and in contact therewith over substantially the entire lateral extents of said first and second regions; f. an electrode for said drain region; g. a source electrode for said third region; h. a first control electrode which is electrically insulated from said surface of the semiconductor at an end of said first region; and i. a second control electrode which is electrically insulated from said surface of the semiconductor at said other end of said second region.

Claim 9

Dependent Claim 75 words

An insulated-gate field effect transistor as claimed in claim 5, in which the region between said first and fourth regions is of the same conductivity type as said fourth region and has an impurity concentration lower than that of said fourth region, and the region between said drain region and said second region is of the same conductivity type as said drain region and has an impurity concentration lower than that of said drain region.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-02-08	1980-08-09	1981-02-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-02-08	1984-08-09	1985-02-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-02-08	1988-08-09	1989-02-08	$7700.00	Window Closed / Lapsed

Field effect transistor

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