US3631312A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-voltage mos transistor method and apparatus
Assignee: National Semiconductor Corp
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Filing: 1969-05-15
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Granted: 1971-12-28
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Expires: 1989-05-15
Abstract
Abstract An MIS FET device and method of making the same wherein a device of nominal topology is made capable of sustaining drain to source potentials substantially higher than the normal breakdown potentials of prior art devices. The present invention is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.
Inventors
- 👤 Kenneth J Moyle
- 👤 Lee P Madden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:32
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/43; H10D; H10D99/00; H10P; H10P95/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
22 words
An improved MIS FET device as recited in claim 1 wherein the depth of said junction is at least 0.2 mil deep.
Claim 2
Dependent Claim
41 words
An improved MIS FET device as recited in claim 1 wherein said substrate is of an N-type impurity and said drain region is of a P-type impurity having a surface concentration of less than 2 X 1018 atoms per cubic centimeter.
Claim 3
Dependent Claim
125 words
An improved MIS FET device having a source-to-drain breakdown voltage exceeding 60 volts comprising: a substrate of a first conductivity type; a drain region of a second conductivity type, which is opposite to said first conductivity type, formed in said substrate and defining an NP junction therewith, the impurity concentration profile in said region being linearly graded at least adjacent said junction; a source region of said second conductivity type formed in said substrate in spaced apart relationship with said drain region; and a gate electrode disposed above the region of said substrate separating said source and drain regions, said gate electrode being positioned to extend over said junction and having an edge disposed between said junction and the inside corner of the depletion region.
Claim 4
Dependent Claim
32 words
An improved MIS FET device as recited in claim 4 in which the impurity concentration at the surface of said drain region is less than 2 X 1018 atoms per cubic centimeter.
Claim 5
Dependent Claim
140 words
An improved MIS FET device having a source-to-drain breakdown voltage exceeding 60 volts comprising: a substrate of a first conductivity type; a drain region of a second conductivity type, which is opposite to said first conductivity type, formed in said substrate and defining an NP junction therewith, the impurity concentration profile in said region being linearly graded at least adjacent said junction; a source region of said second conductivity type formed in said substrate in spaced apart relationship with said drain region; and a gate electrode disposed above the region of said substrate separating said source and drain regions, said gate electrode being positioned to extend over said junction and having an edge overlying said drain region opposite the depletion region across the portion of said junction immediately adjacent the region of said substrate separating said source and drain regions.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-27 | 1975-06-28 | 1975-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-27 | 1979-06-28 | 1979-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-27 | 1983-06-28 | 1983-12-28 | $7700.00 | Window Closed / Lapsed |