Patent US7433237B2 successfully refreshed from Google Patents.
US7433237B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory utilizing oxide nanolaminates
Assignee: Micron Technology Inc
•
Filing: 2006-07-20
•
Granted: 2008-10-07
•
Expires: 2026-07-20
Abstract
Abstract One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:25
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/0466; H10B; H10B69/00; H10D30/00; H10D30/60; H10D30/69; G11C16/0491; H10D64/691; H10D64/693
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
83 words
A transistor device, comprising: a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator; wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; and circuitry coupled to the source/drain regions to program the transistor in a first direction, and read the transistor in a second direction opposite the first direction.
Claim 2
Dependent Claim
83 words
A transistor device, comprising: a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator; wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; and circuitry coupled to the source/drain regions to program the transistor in a first direction, and read the transistor in a second direction opposite the first direction.
Claim 3
Dependent Claim
15 words
The transistor device of claim 1 , wherein the insulator nanolaminate layers include-transition metal oxides.
Claim 4
Dependent Claim
23 words
The transistor device of claim 2 , wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).
Claim 5
Dependent Claim
15 words
The transistor device of claim 1 , wherein the insulator nanolaminate layers include silicon oxycarbide.
Claim 6
Dependent Claim
23 words
The transistor device of claim 4 , wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.
Claim 7
Dependent Claim
125 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one amorphous charge trapping nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a sourceline coupled to the first source/drain region; a transmission line coupled to the second source/drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 8
Dependent Claim
125 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one amorphous charge trapping nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a sourceline coupled to the first source/drain region; a transmission line coupled to the second source/drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 9
Dependent Claim
17 words
The vertical memory cell of claim 6 , wherein the insulator nanolaminate layers includes transition metal oxides.
Claim 10
Dependent Claim
25 words
The vertical memory cell of claim 7 , wherein all the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).
Claim 11
Dependent Claim
16 words
The vertical memory cell of claim 6 , wherein the insulator nanolaminate layers include silicon oxycarbide.
Claim 12
Dependent Claim
24 words
The vertical memory cell of claim 9 , wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.
Claim 13
Dependent Claim
32 words
The vertical memory cell of claim 6 , wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.
Claim 14
Dependent Claim
26 words
The vertical memory cell of claim 6 , further including an electron charge trapped in the amorphous charge trapping nanolaminate layer adjacent the first source/drain region.
Claim 15
Dependent Claim
20 words
The vertical memory cell of claim 6 , wherein the gate insulator has a thickness of approximately 10 nanometers (nm).
Claim 16
Dependent Claim
133 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 17
Dependent Claim
133 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 18
Dependent Claim
23 words
The memory cell of claim 14 , wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).
Claim 19
Dependent Claim
19 words
The memory cell of claim 14 , wherein the gate insulator has a thickness of approximately 10 nanometers (nm).
Claim 20
Dependent Claim
147 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous, at least one nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 21
Dependent Claim
147 words
A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous, at least one nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.
Claim 22
Dependent Claim
23 words
The memory cell of claim 17 , wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.
Claim 23
Dependent Claim
168 words
A transistor array, comprising: a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the transistor array; a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and circuitry coupled to at least one transistor cell to program the transistor cell in a first direction, and read the transistor cell in a second direction opposite the first direction.
Claim 24
Dependent Claim
168 words
A transistor array, comprising: a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the transistor array; a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and circuitry coupled to at least one transistor cell to program the transistor cell in a first direction, and read the transistor cell in a second direction opposite the first direction.
Claim 25
Dependent Claim
16 words
The transistor array of claim 19 , wherein the insulator nanolaminate layers include transition metal oxides.
Claim 26
Dependent Claim
23 words
The transistor array of claim 20 , wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).
Claim 27
Dependent Claim
15 words
The transistor array of claim 19 , wherein the insulator nanolaminate layers include silicon oxycarbide.
Claim 28
Dependent Claim
23 words
The transistor array of claim 22 , wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.
Claim 29
Dependent Claim
27 words
The transistor array of claim 19 , wherein a charge trapped in the charge trapping layer includes a charge adjacent to the source of approximately 100 electrons.
Claim 30
Dependent Claim
33 words
The transistor array of claim 19 , wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.
Claim 31
Dependent Claim
23 words
The transistor array of claim 19 , wherein the gate insulator of each transistor cell has a thickness of approximately 10 nanometers (nm).
Claim 32
Dependent Claim
38 words
The transistor array of claim 19 , wherein the number of transistor cells extending from the substrate operate as equivalent to a transistor having a size equal to or less than 1.0 lithographic feature squared (1F 2 ).
Claim 33
Independent Claim
93 words
A method for forming a transistor device, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; forming a gate over the multilayer gate insulator; and coupling operation circuitry to the source/drain regions to program the transistor in a first direction and to read the transistor in a second direction opposite the first direction.
Claim 34
Independent Claim
93 words
A method for forming a transistor device, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; forming a gate over the multilayer gate insulator; and coupling operation circuitry to the source/drain regions to program the transistor in a first direction and to read the transistor in a second direction opposite the first direction.
Claim 35
Dependent Claim
22 words
The method of claim 28 , wherein forming oxide insulator nanolaminate layers includes forming oxide insulator nanolaminate layers of transition metal oxides.
Claim 36
Dependent Claim
29 words
The method of claim 29 , wherein forming oxide insulator nanolaminate layers of transition metal oxides includes forming transition metal oxide insulator nanolaminate layers using atomic layer deposition (ALD).
Claim 37
Dependent Claim
20 words
The method of claim 28 , wherein forming oxide insulator nanolaminate layers includes forming a nanolaminate layer of silicon oxycarbide.
Claim 38
Dependent Claim
24 words
The method of claim 31 , wherein forming a nanolaminate layer of silicon oxycarbide includes forming a silicon oxycarbide layer using chemical vapor deposition.
References Cited (Backward Citations)
US3665423A
Cited
US3641516A
Cited
US3877054A
Cited
US3978577A
Cited
US3964085A
Cited
US4152627A
Cited
US4173791A
Cited
US4295150A
Cited
US4217601A
Cited
US4507673A
Cited
US4412902A
Cited
US4495219A
Cited
US4939559A
Cited
US4449205A
Cited
US4757360A
Cited
US4717943A
Cited
US4661833A
Cited
JPS61166078A
Cited
US5017977A
Cited
US4829482A
Cited
US4794565A
Cited
US4780424A
Cited
US5016215A
Cited
US4870470A
Cited
US5021999A
Cited
US6630381B1
Cited
US5043946A
Cited
US5293560A
Cited
US4888733A
Cited
US5042011A
Cited
US5111430A
Cited
US5027171A
Cited
JPH03222367A
Cited
US5071782A
Cited
US5073519A
Cited
US5253196A
Cited
US5350738A
Cited
US5677867A
Cited
US5646430A
Cited
US5449941A
Cited
US5332915A
Cited
US5274249A
Cited
US5617351A
Cited
US5399516A
Cited
US5388069A
Cited
US5280205A
Cited
US5317535A
Cited
US5618575A
Cited
US5550770A
Cited
US5409859A
Cited
US5418389A
Cited
US5508544A
Cited
JPH06224431A
Cited
US5438544A
Cited
JPH06302828A
Cited
US5600592A
Cited
US5539279A
Cited
US6521950B1
Cited
US5493140A
Cited
US5298447A
Cited
US5497494A
Cited
US5467306A
Cited
US5557569A
Cited
US5430670A
Cited
US5424993A
Cited
US5541872A
Cited
US5541871A
Cited
US5434815A
Cited
US5508543A
Cited
US5410504A
Cited
US5498558A
Cited
US5485422A
Cited
US5457649A
Cited
US5510278A
Cited
US5455792A
Cited
US5572459A
Cited
US5627781A
Cited
US5445984A
Cited
US5621683A
Cited
US5619642A
Cited
US5600587A
Cited
US5477485A
Cited
JPH08255878A
Cited
US5530668A
Cited
US5530581A
Cited
US5670790A
Cited
US5714766A
Cited
US5627785A
Cited
US5856943A
Cited
US5768192A
Cited
US5912488A
Cited
US5691230A
Cited
US5963476A
Cited
US5801993A
Cited
US5923056A
Cited
US5952692A
Cited
US5959896A
Cited
US6166401A
Cited
US5740104A
Cited
US5754477A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-10-07 | 2012-04-07 | 2012-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-10-07 | 2016-04-07 | 2016-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-10-07 | 2020-04-07 | 2020-10-07 | $7700.00 | Window Closed / Lapsed |