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US7369435B2
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Write once read only memory employing floating gates
Assignee: Micron Technology Inc
•
Filing: 2005-08-30
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Granted: 2008-05-06
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Expires: 2025-08-30
Abstract
Abstract Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A plug couples the first source/drain region to an array plate. A bitline is coupled to the second source/drain region. The floating gate transistor can be programmed by trapping charge on the floating gate.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:25
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
170 words
A method of forming a memory cell, comprising: forming a floating gate transistor in a modified dynamic random access memory fabrication process, wherein forming the floating gate transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming an array plate; forming a conductive plug coupling the first source/drain region to the array plate; and forming a bitline coupled to the second source/drain region such that the memory cell can be programmed to have a trapped charge in the floating gate by biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.
Claim 2
Independent Claim
170 words
A method of forming a memory cell, comprising: forming a floating gate transistor in a modified dynamic random access memory fabrication process, wherein forming the floating gate transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming an array plate; forming a conductive plug coupling the first source/drain region to the array plate; and forming a bitline coupled to the second source/drain region such that the memory cell can be programmed to have a trapped charge in the floating gate by biasing the array plate to a voltage higher than VDD, grounding the bitline, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.
Claim 3
Dependent Claim
29 words
The method of claim 1 , wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
Claim 4
Independent Claim
110 words
A method of forming a memory cell, comprising: forming a transistor, wherein forming the transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and forming reading circuitry to read the transistor in a forward direction.
Claim 5
Independent Claim
110 words
A method of forming a memory cell, comprising: forming a transistor, wherein forming the transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and forming reading circuitry to read the transistor in a forward direction.
Claim 6
Dependent Claim
20 words
The method of claim 3 , wherein the memory cell is formed using substantially dynamic random access memory fabrication processes.
Claim 7
Dependent Claim
52 words
The method of claim 3 , wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
Claim 8
Dependent Claim
20 words
The method of claim 3 , wherein forming programming circuitry includes coupling an array plate to the first source/drain region.
Claim 9
Dependent Claim
28 words
The method of claim 3 , wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of approximately 10 nanometers (nm).
Claim 10
Dependent Claim
22 words
The method of claim 3 , wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
Claim 11
Independent Claim
126 words
A method of forming a memory array, comprising: forming an array of transistors, wherein forming at least one transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming a wordline coupled to control gates in the array of transistors; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and forming reading circuitry to read the transistor in a forward direction.
Claim 12
Independent Claim
126 words
A method of forming a memory array, comprising: forming an array of transistors, wherein forming at least one transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming a wordline coupled to control gates in the array of transistors; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; and forming reading circuitry to read the transistor in a forward direction.
Claim 13
Dependent Claim
27 words
The method of claim 9 , wherein forming programming circuitry includes coupling an array plate to the first source/drain regions of transistors in the array of transistors.
Claim 14
Dependent Claim
29 words
The method of claim 9 , wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
Claim 15
Dependent Claim
22 words
The method of claim 9 , wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
Claim 16
Dependent Claim
52 words
The method of claim 9 , wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
Claim 17
Dependent Claim
20 words
The method of claim 9 , wherein the memory array is formed using substantially dynamic random access memory fabrication processes.
Claim 18
Independent Claim
146 words
A method of forming an electronic system, comprising: forming a memory array including a plurality of transistors, wherein forming at least one transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming a wordline coupled to control gates in the array of transistors; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; forming reading circuitry to read the transistor in a forward direction; forming a bus coupled to the memory array; and coupling the array of transistors to a processor.
Claim 19
Independent Claim
146 words
A method of forming an electronic system, comprising: forming a memory array including a plurality of transistors, wherein forming at least one transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a floating gate above the gate insulator; forming a gate dielectric on the floating gate; forming a control gate on the gate dielectric; forming a wordline coupled to control gates in the array of transistors; forming programming circuitry to create a hot electron injection into the floating gate adjacent to the first source/drain region in a reverse direction of the transistor; forming reading circuitry to read the transistor in a forward direction; forming a bus coupled to the memory array; and coupling the array of transistors to a processor.
Claim 20
Dependent Claim
52 words
The method of claim 15 , wherein forming programming circuitry includes forming circuitry to apply a first voltage potential greater than VDD to the first source/drain region and forming circuitry to apply a ground potential to the second source/drain region, and forming circuitry to apply a gate potential to the control gate.
Claim 21
Dependent Claim
42 words
The method of claim 15 , wherein forming reading circuitry includes forming circuitry to apply a ground potential to the first source/drain region, and forming circuitry to apply a fractional voltage of VDD to the second source/drain region during a reading operation.
Claim 22
Dependent Claim
27 words
The method of claim 15 , wherein forming programming circuitry includes coupling an array plate to the first source/drain regions of transistors in the array of transistors.
Claim 23
Dependent Claim
29 words
The method of claim 15 , wherein forming the gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
Claim 24
Dependent Claim
20 words
The method of claim 15 , wherein the memory array is formed using substantially dynamic random access memory fabrication processes.
Claim 25
Dependent Claim
22 words
The method of claim 15 , wherein forming the gate insulator above the channel region includes forming a silicon dioxide gate insulator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-05-06 | 2011-11-05 | 2012-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-05-06 | 2015-11-05 | 2016-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-05-06 | 2019-11-05 | 2020-05-06 | $7700.00 | Window Closed / Lapsed |