Patent US1748739A successfully refreshed from Google Patents.
Patent US6407576B1 successfully refreshed from Google Patents.
US6407576B1
Expired / Lapsed
US
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Interconnection and input/output resources for programmable logic integrated circuit devices
Assignee: Altera Corp
•
Filing: 2000-03-02
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Granted: 2002-06-18
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Expires: 2020-03-02
Abstract
Abstract A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
Inventors
- 👤 Tony Ngai
- 👤 Bruce Pedersen
- 👤 Sergey Shumarayev
- 👤 James Schleicher
- 👤 Wei-Jen Huang
- 👤 Michael Hutton
- 👤 Victor Maruri
- 👤 Rakesh Patel
- 👤 Peter J. Kazarian
- 👤 Andrew Leaver
- 👤 David W. Mendel
- 👤 Jim Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:03
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/177; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1774; H03K19/17744; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
207 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the high-speed portion includes a plurality of interconnection conductors, each being associated with circuitry that can programmably select any of at least a subplurality of the output terminals of the logic regions for connection to that interconnection conductor.
Claim 2
Dependent Claim
207 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the high-speed portion includes a plurality of interconnection conductors, each being associated with circuitry that can programmably select any of at least a subplurality of the output terminals of the logic regions for connection to that interconnection conductor.
Claim 3
Dependent Claim
255 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the second high-speed portion is configured to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions by providing signal routing which is alternative to at least part of routing for the same connection through the first normal-speed portion, the alternative routing through the second high-speed portion being substantially faster than routing through the first normal-speed portion to which the alternative routing is alternative.
Claim 4
Dependent Claim
255 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the second high-speed portion is configured to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions by providing signal routing which is alternative to at least part of routing for the same connection through the first normal-speed portion, the alternative routing through the second high-speed portion being substantially faster than routing through the first normal-speed portion to which the alternative routing is alternative.
Claim 5
Dependent Claim
288 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the regions are disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, wherein the interconnection network includes a group of horizontal interconnection conductors associated with and extending along each of the rows, a group of vertical interconnection conductors associated with and extending along each of the columns, and programmable connectors configured to selectively interconnect horizontal and vertical interconnection conductors, and wherein a first subset of the conductors in each of the groups is configured to form part of the first normal-speed portion of the interconnection network, and a second subset of the conductors in each of the groups is configured to form part of the second high-speed portion of the interconnection network.
Claim 6
Dependent Claim
288 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the regions are disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, wherein the interconnection network includes a group of horizontal interconnection conductors associated with and extending along each of the rows, a group of vertical interconnection conductors associated with and extending along each of the columns, and programmable connectors configured to selectively interconnect horizontal and vertical interconnection conductors, and wherein a first subset of the conductors in each of the groups is configured to form part of the first normal-speed portion of the interconnection network, and a second subset of the conductors in each of the groups is configured to form part of the second high-speed portion of the interconnection network.
Claim 7
Dependent Claim
31 words
The device defined in claim 3 wherein the first subset in each of the groups includes more of the conductors of that group than the second subset of that group includes.
Claim 8
Dependent Claim
31 words
The device defined in claim 4 wherein the first subset in each of the groups includes in the range from about 67% to about 80% of the conductors in that group.
Claim 9
Dependent Claim
49 words
The device defined in claim 3 wherein the programmable connectors include a first subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the first subsets of the conductors but not horizontal and vertical interconnection conductors in the second subsets of the conductors.
Claim 10
Dependent Claim
49 words
The device defined in claim 3 wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.
Claim 11
Dependent Claim
49 words
The device defined in claim 6 wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.
Claim 12
Dependent Claim
44 words
The device defined in claim 8 wherein each of the programmable connectors includes a signal driver, and wherein the signal drivers of the second subset of the connectors are larger and more powerful than the signal drivers of the first subset of the connectors.
Claim 13
Dependent Claim
36 words
The device defined in claim 3 wherein the conductors in the second subset of the conductors in each of the groups are wider than the conductors in the first subset of the conductors in that group.
Claim 14
Dependent Claim
41 words
The device defined in claim 3 wherein the conductors in the second subset of the conductors in each of the groups are spaced more widely from other conductors than the conductors in the first subset of the conductors in that group.
Claim 15
Dependent Claim
196 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the output terminal of each of the regions is substantially directly connectable to both the first normal-speed portion and the second high-speed portion of the interconnection network.
Claim 16
Dependent Claim
196 words
A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, the interconnection network including a first normal-speed portion which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions, and a second high-speed portion which is programmable to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions, wherein the output terminal of each of the regions is substantially directly connectable to both the first normal-speed portion and the second high-speed portion of the interconnection network.
Claim 17
Dependent Claim
82 words
The device defined in claim 3 wherein the interconnection network further includes programmable circuitry configured to apply signals from at least some of the interconnection conductors associated with each of the regions to at least one input terminal of that region, the programmable circuitry including connection paths that are more direct for signals from conductors in the second subset of the conductors associated with that region than for signals from conductors in the first subset of the conductors associated with that region.
Claim 18
Dependent Claim
35 words
The device defined in claim 3 further comprising: a plurality of high-speed regional interconnection conductors associated with and extending along each of a plurality of subsets of multiple adjacent regions in each of the rows.
Claim 19
Dependent Claim
46 words
The device defined in claim 14 wherein each of the high-speed regional interconnection conductors is configured for programmable connection to the output terminal of the one of the associated regions that is approximately centered amid the multiple adjacent regions associated with that high-speed regional interconnection conductor.
Claim 20
Dependent Claim
40 words
The device defined in claim 15 wherein each of the high-speed regional interconnection conductors associated with each region is programmably connectable to at least one input terminal of substantially any of the regions associated with that high-speed local interconnection conductor.
Claim 21
Dependent Claim
85 words
The device defined in claim 3 further comprising a bridging interconnection conductor associated with each adjacent pair of regions in each column and configured to convey a signal from one of the regions in the associated pair only to programmable output circuitry associated with the other region in that pair, the output circuitry being configured to selectively apply a signal on the bridging interconnection conductor to the interconnection network in lieu of the signal from the output terminal of the other region in that pair.
Claim 22
Dependent Claim
32 words
A digital processing system comprising: processing circuitry; a memory coupled to the processing circuitry; and a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
Claim 23
Dependent Claim
18 words
A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
Claim 24
Dependent Claim
25 words
The printed circuit board defined in claim 19 further comprising: a memory mounted on the printed circuit board and coupled to the programmable logic device.
Claim 25
Dependent Claim
25 words
The printed circuit board defined in claim 19 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
Claim 26
Dependent Claim
93 words
The device defined in claim 1 wherein the second high-speed portion is configured to optionally make at least part of a connection between the output terminal of substantially any of the regions and at least one of the input terminals of substantially any of the regions by providing signal routing which is alternative to at least part of routing for the same connection through the first normal-speed portion, the alternative routing through the second high-speed portion being substantially faster than routing through the first normal-speed portion to which the alternative routing is alternative.
Claim 27
Dependent Claim
126 words
The device defined in claim 1 wherein the regions are disposed on the device in a two-dimensional array of intersecting rows and columns of the regions, wherein the interconnection network includes a group of horizontal interconnection conductors associated with and extending along each of the rows, a group of vertical interconnection conductors associated with and extending along each of the columns, and programmable connectors configured to selectively interconnect horizontal and vertical interconnection conductors, and wherein a first subset of the conductors in each of the groups is configured to form part of the first normal-speed portion of the interconnection network, and a second subset of the conductors in each of the groups is configured to form part of the second high-speed portion of the interconnection network.
Claim 28
Dependent Claim
31 words
The device defined in claim 23 wherein the first subset in each of the groups includes more of the conductors of that group than the second subset of that group includes.
Claim 29
Dependent Claim
31 words
The device defined in claim 24 wherein the first subset in each of the groups includes in the range from about 67% to about 80% of the conductors in that group.
Claim 30
Dependent Claim
49 words
The device defined in claim 23 wherein the programmable connectors include a first subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the first subsets of the conductors but not horizontal and vertical interconnection conductors in the second subsets of the conductors.
Claim 31
Dependent Claim
49 words
The device defined in claim 23 wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.
Claim 32
Dependent Claim
49 words
The device defined in claim 26 wherein the programmable connectors include a second subset of the connectors that are configured to selectively interconnect horizontal and vertical interconnection conductors in the second subsets of the conductors but not horizontal and vertical interconnection conductors in the first subsets of the conductors.
Claim 33
Dependent Claim
44 words
The device defined in claim 28 wherein each of the programmable connectors includes a signal driver, and wherein the signal drivers of the second subset of the connectors are larger and more powerful than the signal dirvers of the first subset of the connectors.
Claim 34
Dependent Claim
36 words
The device defined in claim 23 wherein the conductors in the second subset of the conductors in each of the groups are wider than the conductors in the first subset of the conductors in that group.
Claim 35
Dependent Claim
41 words
The device defined in claim 23 wherein the conductors in the second subset of the conductors in wach of the groups are spaced more widely from other conductors than the conductors in the first subset of the conductors in that group.
Claim 36
Dependent Claim
34 words
The device defined in claim 1 wherein the output terminal of each of the regions is substantially directly connectable to both the first normal-speed portion and the second high-speed portion of the interconnection network.
Claim 37
Dependent Claim
82 words
The device defined in claim 23 wherein the interconnection network further includes programmable circuitry configured to apply signals from at least some of the interconnection conductors associated with each of the regions to at least one input terminal of that region, the programmable circuitry including connection paths that are more direct for signals from conductors in the second subset of the conductors associated with the region than for signals from conductors in the first subset of the conductors associated with that region.
Claim 38
Dependent Claim
35 words
The device defined in claim 23 further comprising: a plurality of high-speed regional interconnection conductors associated with and extending along each of a plurality of subsets of multiple adjacent regions in each of the rows.
Claim 39
Dependent Claim
46 words
The device defined in claim 34 wherein each of the high-speed regional interconnection conductors is configured for programmable connection to the output terminal of the one of the associated regions that is approximately centered amid the multiple adjacent regions associated with that high-speed regional interconnection conductor.
Claim 40
Dependent Claim
40 words
The device defined in claim 35 wherein each of the high-speed regional interconnection conductors associated with each region is programmably connectable to at least one input terminal of substantially any of the regions associated with that high-speed local interconnection conductor.
Claim 41
Dependent Claim
85 words
The device defined in claim 23 further comprising a bridging interconnection conductor associated with each adjacent pair of regions in each column and configured to convey a signal from one of the regions in the associated pair only to programmable output circuitry associated with the other region in that pair, the output circuitry being configured to selectively apply a signal on the bridging interconnection conductor to the interconnection network in lieu of the signal from the output terminal of the other region in that pair.
Claim 42
Dependent Claim
32 words
A digital processing system comprising: processing circuitry; a memory coupled to the processing circuitry; and a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
Claim 43
Dependent Claim
18 words
A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
Claim 44
Dependent Claim
25 words
The printed circuit board defined in claim 39 further comprising: a memory mounted on the printed circuit board and coupled to the programmable logic device.
Claim 45
Dependent Claim
25 words
The printed circuit board defined in claim 39 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-17 | 2005-12-17 | 2006-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-17 | 2009-12-17 | 2010-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-17 | 2013-12-17 | 2014-06-18 | $7700.00 | Window Closed / Lapsed |