EP0630115A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Configurable logic array
Assignee: Motorola Solutions Inc
•
Filing: 1994-06-01
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Granted: —
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Expires: 2014-06-01
Abstract
Abstract A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:- (i) global connection parts (G,X) having selectable connections with the porting arrangement of each zone, (ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising a restricted signal translation system. The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function.
Inventors
- 👤 Gareth James Jones
- 👤 Gordon Stirling Work
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/17704; H03K19/1774; H03K19/17744; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 63
Claim 1
Independent Claim
228 words
A semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (CC) respectively defining a matrix array of cells, characterised in that the matrix array of cells is sub-divided at least into zones (11) each comprising a matrix array of said cells and further comprising a porting arrangement (VPC, HPC) for each zone, the integrated circuit as made having an hierarchical routing resource structure comprising:- (i) global connection paths (G) which extend continuously across more than one zone and have selectable connections with the porting arrangement of at least some of the zones, (ii) medium connection paths (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising for each cell a restricted signal translation system between inputs and outputs of the cells each selectable as to its conduction state, those paths extending for each said logic circuit from its output to inputs of a first set of some of other said logic circuits and from its inputs to outputs of a second set of some of other said logic circuits, each first set of logic circuits being different from any other first set of logic circuits, and each second set of logic circuits being different from any other second set of logic circuit.
Claim 2
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in claim 1 in which the zones are arranged in a matrix array (11) of zones.
Claim 3
Dependent Claim
30 words
A semi-conductor integrated circuit as claimed in claim 1 or 2 in which the plurality of zones define a quadrant (13) and the integrated circuit has a plurality of quadrants.
Claim 4
Dependent Claim
19 words
A semi-conductor integrated circuit as claimed in claim 3 in which the quadrants are arranged in a matrix array.
Claim 5
Dependent Claim
34 words
A semi-conductor integrated circuit as claimed in claims 1 to 5 in which there are 10 x 10 cells to a zone, 5 x 5 zones to a quadrant and 2 x 2 quadrants.
Claim 6
Dependent Claim
30 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which the global connection paths (G1...4H, G1...4V) extend horizontally and vertically across a plurality of zones.
Claim 7
Dependent Claim
33 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which there are a plurality of global connection paths for each row and column of cells in a zone.
Claim 8
Dependent Claim
25 words
A semi-conductor integrated circuit as claimed in claim 7 in which there are four global (G1...4) connection paths for each row and column of cells.
Claim 9
Dependent Claim
34 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which there are a plurality of medium connection paths (M) for each row and column of cells of a zone.
Claim 10
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in claim 9 in which there are four medium connection paths for each row and column.
Claim 11
Dependent Claim
32 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which each medium connection path is selectably connectable with an output and/or input of one or more cells.
Claim 12
Dependent Claim
45 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims and comprising further global routing resources comprising horizontal and vertical buses (X) extending across a zone horizontally and vertically respectively, and which are connectable with the port cells and with one another.
Claim 13
Dependent Claim
23 words
A semi-conductor integrated circuit as claimed in claim 12 in which the further horizontal and vertical buses are not connectable to the cells.
Claim 14
Dependent Claim
28 words
A semi-conductor integrated circuit as claimed in claim 12 or 13 in which there is one such further global connection bus for each row and column of cells.
Claim 15
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 14 in which there is a connection between the horizontal and vertical buses for each cell.
Claim 16
Dependent Claim
45 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims comprising horizontal and vertical port cells (HPC, VPC), the porting arrangement of which permits resources to be routed from the global lines through to the medium lines and thereby into the cells.
Claim 17
Dependent Claim
40 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which the general interconnect structure (global and medium buses) are interconnectable with special interconnect structure, for example clocks and tristates, by way of the port cells.
Claim 18
Dependent Claim
67 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims further comprising clock distribution channels, preferably comprising a vertical clock bus (with say 8 lines) extending between clock pads (CP) to top and bottom of the array, a horizontal clock distribution spine (HCS) (with say 8 lines), extending between clock pads to opposite sides of the array and intersecting with the vertical clock bus.
Claim 19
Dependent Claim
46 words
A semi-conductor integrated circuit as claimed in claim 18 in which there is a vertical clock distribution spine (VCS) for each zone (conveniently tapped off from the horizontal clock spine) by which clock and reset signals are distributed to the vertical port cell of that zone.
Claim 20
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in claim 18 or 19 in which alternate core cells have clock and reset signal lines.
Claim 21
Dependent Claim
66 words
A semi-conductor integrated circuit as claimed in any one of the preceding claims in which each cell has a common logic function and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles (T) comprising a matrix array of the core cells (CC) and wherein each tile has at least one of each different subsidiary functions.
Claim 22
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 21 in which the different subsidiary functions comprise:- wired-OR; XOR; D-type flip flop and latch functions.
Claim 23
Dependent Claim
44 words
A semi-conductor integrated circuit as claimed in claims 21 or 22 when appended to claim 16 comprising dedicated connection lines with the horizontal port cell (specifically wired -OR buses (say 5)) running across each zone and connecting directly with the wired -OR core cells.
Claim 24
Dependent Claim
37 words
A semi-conductor integrated circuit as claimed in claim 23 in which connection of the wired -OR buses may be made to a certain (restricted) number of global buses, for example by way of the horizontal port cells.
Claim 25
Dependent Claim
33 words
A semi-conductor integrated circuit as claimed in claim 17 when appendant to claim 12 in which there are wired -OR connections between the further global horizontal buses and say three horizontal global buses.
Claim 26
Dependent Claim
91 words
A configurable semi-conductor integrated circuit comprising a matrix array of core cells (CC) each of the cells having a first simple function in common and at least one subsidiary function, characterised in that there are at least two different subsidiary functions, the core cells are grouped in tiles (T) comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions, and wherein the tiles of core cells are arranged so as to uniformly cover the array.
Claim 27
Dependent Claim
26 words
A configurable semi-conductor integrated circuit claimed in claim 26 in which the arrangement of the subsidiary functions within the cells of the tile are substantially different.
Claim 28
Dependent Claim
245 words
A configurable semi-conductor integrated circuit which comprises an area thereof formed with a plurality of logic circuits at discrete sites or cells respectively, each said logic circuit having in common a restricted simple logic function capability and itself only being capable of implementing a simple logic function, and the cell having a restricted signal translation system between inputs and outputs of the logic circuits affording (local) direct connection paths each selectable as to its conduction state, those paths extending, for each said logic circuit, from its output to inputs of first set of some of other said logic circuits and from its inputs to outputs of a second set of some of other said logic circuits, each first set of logic circuits being different from any other first set of logic circuits, and each second set of logic circuits being different from any other second set of logic circuits, the integrated circuit further comprises at each discrete site or cell additional optionally selectable circuit configurations selectively controlled by control means to enable each cell to operate in a selected one of two or more ways, characterised in that there are a plurality of different optional circuit configurations and wherein the cells are arranged in groups, hereinafter referred to as tiles (T) smaller than the whole array, with each tile having at least one of each of the different circuit configurations, and wherein the tiles of cells are arranged so as to uniformly cover the array.
Claim 29
Dependent Claim
41 words
A semi-conductor integrated circuit as claimed in claim 28 in which the selected one of two or more ways comprises either the simple logic function common to each cell or a selected subsidiary function afforded by the optionally selectable circuit configurations.
Claim 30
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claims 21 or 26 to 29 in which the common simple logic function is a NAND gate.
Claim 31
Dependent Claim
44 words
A semi-conductor integrated circuit as claimed in claims 26 to 30 in which the optionally selectable circuit configurations (different subsidiary functions) afford optional functions of:- wired -OR output buffer; XOR; D-type flip flop (with reset and enable) and latch function (with reset and enable).
Claim 32
Dependent Claim
36 words
A semi-conductor integrated circuit as claimed in any one of claims 26 to 31 in which some cells may have additional circuit configurations to facilitate by virtue of the tile arrangement building up higher level functions.
Claim 33
Dependent Claim
21 words
A semi-conductor integrated circuit as claimed in claim 22 or 31 in which there are two XOR functions to a tile.
Claim 34
Dependent Claim
26 words
A semi-conductor integrated circuit as claimed in claim 22, 31 or 32 in which one cell offers optionally two functions (preferably the D-flip flop and latch).
Claim 35
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in any one of claims 22, 26 to 34 in which the tile comprises four cells.
Claim 36
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 35 in which the four cells are arranged in a matrix of 2 x 2 cells.
Claim 37
Dependent Claim
26 words
A semi-conductor integrated circuit a claimed in claim 28 in which the arrangement of the subsidiary functions within the cells of the tile are substantially different.
Claim 38
Dependent Claim
252 words
A semi-conductor integrated circuit as claimed in claims 26 or 27 or any one of claims 30 to 36 when appendant to claim 26 or 27 in which an area thereof is formed with a plurality of logic circuits at discrete sites or cells (CC) respectively defining said matrix array of cells, characterised in that the matrix array of cells is sub-divided at least into zones (11) each comprising a matrix array of said cells and further comprising a porting arrangement (VPC, HPC) for each zone, the integrated circuit as made having an hierarchical routing resource structure comprising:- (i) global connection paths (G) which extend continuously across more than one zone and have selectable connections with the porting arrangement of at least some of the zones, (ii) medium connection paths (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising for each cell a restricted signal translation system between inputs and outputs of the cells each selectable as to its conduction state, those paths extending for each said logic circuit from its output to inputs of a first set of some of other said logic circuits and from its inputs to outputs of a second set of some of other said logic circuits, each first set of logic circuits being different from any other first set of logic circuits, and each second set of logic circuits being different from any other second set of logic circuit.
Claim 39
Dependent Claim
146 words
A semi-conductor integrated circuit as claimed in claim 28 or any one of claims 29 to 36 when appendant to claim 28 in which the plurality of logic circuits at discrete sites or cells (CC) respectively define a matrix array of cells, characterised in that the matrix array of cells is sub-divided at least into zones (11) each comprising a matrix array of said cells and further comprising a porting arrangement (VPC, HPC) for each zone, the integrated circuit as made having an hierarchical routing resource structure comprising:- (i) global connection paths (G) which extend continuously across more than one zone and have selectable connections with the porting arrangement of at least some of the zones, (ii) medium connection paths (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) said local direct connection paths.
Claim 40
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 38 or 39 in which the zones are arranged in a matrix array (11) of zones.
Claim 41
Dependent Claim
31 words
A semi-conductor integrated circuit as claimed in claim 38, 39 or 40 in which the plurality of zones define a quadrant (13) and the integrated circuit has a plurality of quadrants.
Claim 42
Dependent Claim
19 words
A semi-conductor integrated circuit as claimed in claim 41 in which the quadrants are arranged in a matrix array.
Claim 43
Dependent Claim
34 words
A semi-conductor integrated circuit as claimed in claims 38 to 42 in which there are 10 x 10 cells to a zone, 5 x 5 zones to a quadrant and 2 x 2 quadrants.
Claim 44
Dependent Claim
31 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 43 in which the global connection paths (G1...4H, G1...4V) extend horizontally and vertically across a plurality of zones.
Claim 45
Dependent Claim
34 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 44 in which there are a plurality of global connection paths for each row and column of cells in a zone.
Claim 46
Dependent Claim
25 words
A semi-conductor integrated circuit as claimed in claim 45 in which there are four global (G1...4) connection paths for each row and column of cells.
Claim 47
Dependent Claim
35 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 46 in which there are a plurality of medium connection paths (M) for each row and column of cells of a zone.
Claim 48
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in claim 47 in which there are four medium connection paths for each row and column.
Claim 49
Dependent Claim
33 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 48 in which each medium connection path is selectably connectable with an output and/or input of one or more cells.
Claim 50
Dependent Claim
46 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 49 and comprising further global routing resources comprising horizontal and vertical buses (X) extending across a zone horizontally and vertically respectively, and which are connectable with the port cells and with one another.
Claim 51
Dependent Claim
23 words
A semi-conductor integrated circuit as claimed in claim 50 in which the further horizontal and vertical buses are not connectable to the cells.
Claim 52
Dependent Claim
28 words
A semi-conductor integrated circuit as claimed in claim 50 or 51 in which there is one such further global connection bus for each row and column of cells.
Claim 53
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 52 in which there is a connection between the horizontal and vertical buses for each cell.
Claim 54
Dependent Claim
46 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 53 comprising horizontal and vertical port cells (HPC, VPC), the porting arrangement of which permits resources to be routed from the global lines through to the medium lines and thereby into the cells.
Claim 55
Dependent Claim
41 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 54 in which the general interconnect structure (global and medium buses) are interconnectable with special interconnect structure, for example clocks and tristates, by way of the port cells.
Claim 56
Dependent Claim
68 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 55 further comprising clock distribution channels, preferably comprising a vertical clock bus (with say 8 lines) extending between clock pads (CP) to top and bottom of the array, a horizontal clock distribution spine (HCS) (with say 8 lines), extending between clock pads to opposite sides of the array and intersecting with the vertical clock bus.
Claim 57
Dependent Claim
46 words
A semi-conductor integrated circuit as claimed in claim 56 in which there is a vertical clock distribution spine (VCS) for each zone (conveniently tapped off from the horizontal clock spine) by which clock and reset signals are distributed to the vertical port cell of that zone.
Claim 58
Dependent Claim
22 words
A semi-conductor integrated circuit as claimed in claim 56 or 57 in which alternate core cells have clock and reset signal lines.
Claim 59
Dependent Claim
67 words
A semi-conductor integrated circuit as claimed in any one of claims 38 to 58 in which each cell has a common logic function and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles (T) comprising a matrix array of the core cells (CC) and wherein each tile has at least one of each different subsidiary functions.
Claim 60
Dependent Claim
24 words
A semi-conductor integrated circuit as claimed in claim 59 in which the different subsidiary functions comprise:- wired-OR; XOR; D-type flip flop and latch functions.
Claim 61
Dependent Claim
44 words
A semi-conductor integrated circuit as claimed in claims 59 or 60 when appended to claim 54 comprising dedicated connection lines with the horizontal port cell (specifically wired -OR buses (say 5)) running across each zone and connecting directly with the wired -OR core cells.
Claim 62
Dependent Claim
37 words
A semi-conductor integrated circuit as claimed in claim 61 in which connection of the wired -OR buses may be made to a certain (restricted) number of global buses, for example by way of the horizontal port cells.
Claim 63
Dependent Claim
33 words
A semi-conductor integrated circuit as claimed in claim 55 when appendant to claim 50 in which there are wire -OR connections between the further global horizontal buses and say three horizontal global buses.
References Cited (Backward Citations)
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