US5381058A
Expired / Lapsed
US
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FPGA having PFU with programmable output driver inputs
Assignee: Lattice Semiconductor Corp
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Filing: 1993-05-21
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Granted: 1995-01-10
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Expires: 2013-05-21
Abstract
Abstract In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.
Inventors
- 👤 Barry K. Britton
- 👤 Dwight D. Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
132 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit having a plurality of logic circuits and a plurality of output drivers, each of said plurality of logic circuits having an output, each of said plurality of output drivers having an input adapted to be selectively coupled to any of the outputs of the plurality of logic circuits, one of said plurality of logic circuits comprising a sequential logic circuit; and a programmable interconnection adapted to selectively couple the input of each of the plurality of output drivers to the output of a selected one of the plurality of logic circuits, whereby any of the logic circuit outputs may be coupled as an input to any one of the output drivers.
Claim 2
Dependent Claim
132 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit having a plurality of logic circuits and a plurality of output drivers, each of said plurality of logic circuits having an output, each of said plurality of output drivers having an input adapted to be selectively coupled to any of the outputs of the plurality of logic circuits, one of said plurality of logic circuits comprising a sequential logic circuit; and a programmable interconnection adapted to selectively couple the input of each of the plurality of output drivers to the output of a selected one of the plurality of logic circuits, whereby any of the logic circuit outputs may be coupled as an input to any one of the output drivers.
Claim 3
Dependent Claim
18 words
A field programmable gate array as recited in claim 1, wherein the sequential logic circuit is a latch.
Claim 4
Dependent Claim
20 words
A field programmable gate array as recited in claim 1, wherein the sequential logic circuit is configurable as a latch.
Claim 5
Dependent Claim
18 words
A field programmable gate array as recited in claim 1, wherein the sequential logic circuit is a flip-flop.
Claim 6
Dependent Claim
20 words
A field programmable gate array as recited in claim 1, wherein the sequential logic circuit is configurable as a flip-flop.
Claim 7
Dependent Claim
30 words
A field programmable gate array as recited in claim 1, wherein each output driver further comprises an output, each output driver output providing an output from the programmable function unit.
Claim 8
Dependent Claim
26 words
A field programmable gate array as recited in claim 1, wherein the plurality of logic circuits is different in number than the plurality of output drivers.
Claim 9
Dependent Claim
24 words
A field programmable gate array as recited in claim 7, wherein the number of output drivers is less than the number of logic circuits.
Claim 10
Dependent Claim
23 words
A field programmable gate array as recited in claim 1, wherein one of said plurality of logic circuit comprises a combinatorial logic circuit.
Claim 11
Dependent Claim
19 words
A field programmable gate array as recited in claim 9, wherein the combinatorial logic circuit is a look-up table.
Claim 12
Dependent Claim
119 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit having a plurality of logic circuits and a plurality of output drivers, each of said plurality of logic circuits having an output, each of said plurality of output drivers having an input adapted to be selectively coupled to any of the outputs of the plurality of logic circuits; and a multiplexer adapted to selectively couple the input of each of the plurality of output drivers to the output of a selected one of the plurality of logic circuits, whereby any of the logic circuit outputs may be coupled as an input to any one of the output drivers.
Claim 13
Dependent Claim
119 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit having a plurality of logic circuits and a plurality of output drivers, each of said plurality of logic circuits having an output, each of said plurality of output drivers having an input adapted to be selectively coupled to any of the outputs of the plurality of logic circuits; and a multiplexer adapted to selectively couple the input of each of the plurality of output drivers to the output of a selected one of the plurality of logic circuits, whereby any of the logic circuit outputs may be coupled as an input to any one of the output drivers.
Claim 14
Dependent Claim
30 words
A field programmable gate array as recited in claim 11, wherein each output driver further comprises an output, each output driver output providing an output from the programmable function unit.
Claim 15
Dependent Claim
26 words
A field programmable gate array as recited in claim 11, wherein the plurality of logic circuits is different in number than the plurality of output drivers.
Claim 16
Dependent Claim
24 words
A field programmable gate array as recited in claim 13, wherein the number of output drivers is less than the number of logic circuits.
Claim 17
Dependent Claim
23 words
A field programmable gate array as recited in claim 11, wherein one of said plurality of logic circuits comprises a combinatorial logic circuit.
Claim 18
Dependent Claim
19 words
A field programmable gate array as recited in claim 15, wherein the combinatorial logic circuit is a look-up table.
Claim 19
Dependent Claim
106 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit comprising a first logic circuit providing a first logic circuit output, a second logic circuit providing a second logic circuit output, a first output driver having an input, and a second output driver having an input; and a programmable interconnection adapted to selectively couple the input of the first output driver and the input of the second output drive to the output of at least one of the first and second logic circuits, at least one of said logic circuits comprising a sequential logic circuit.
Claim 20
Dependent Claim
106 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit comprising a first logic circuit providing a first logic circuit output, a second logic circuit providing a second logic circuit output, a first output driver having an input, and a second output driver having an input; and a programmable interconnection adapted to selectively couple the input of the first output driver and the input of the second output drive to the output of at least one of the first and second logic circuits, at least one of said logic circuits comprising a sequential logic circuit.
Claim 21
Dependent Claim
18 words
A field programmable gate array as recited in claim 17, wherein the sequential logic circuit is a latch.
Claim 22
Dependent Claim
20 words
A field programmable gate array as recited in claim 17, wherein the sequential logic circuit is configurable as a latch.
Claim 23
Dependent Claim
18 words
A field programmable gate array as recited in claim 17, wherein the sequential logic circuit is a flip-flop.
Claim 24
Dependent Claim
20 words
A field programmable gate array as recited in claim 17, wherein the sequential logic circuit is configurable as a flip-flop.
Claim 25
Dependent Claim
21 words
A field programmable gate array as recited in claim 17, wherein one of said logic circuits comprises a combinatorial logic circuit.
Claim 26
Dependent Claim
19 words
A field programmable gate array as recited in claim 22, wherein the combinatorial logic circuit is a look-up table.
Claim 27
Dependent Claim
45 words
A field programmable gate array as recited in claim 17, wherein the first output driver further comprises an output, and wherein the second output driver further comprises an output, the outputs from the first and second output drivers providing outputs from the programmable function unit.
Claim 28
Dependent Claim
92 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit comprising a first logic circuit providing a first logic circuit output, a second logic circuit providing a second logic circuit output, a first output driver having input, and a second output driver having an input; and a multiplexer adapted to selectively couple the input of the first output driver and the input of the second output driver to the output of at least one of the first and second logic circuits.
Claim 29
Dependent Claim
92 words
A field programmable gate array, comprising: at least one programmable function unit, each of said at least one programmable function unit comprising a first logic circuit providing a first logic circuit output, a second logic circuit providing a second logic circuit output, a first output driver having input, and a second output driver having an input; and a multiplexer adapted to selectively couple the input of the first output driver and the input of the second output driver to the output of at least one of the first and second logic circuits.
Claim 30
Dependent Claim
24 words
A field programmable gate array as recited in claim 25, wherein the programmable interconnection further comprises configurable interconnect points to achieve the selective coupling.
Claim 31
Dependent Claim
21 words
A field programmable gate array as recited in claim 25, wherein one of said logic circuits comprises a combinatorial logic circuit.
Claim 32
Dependent Claim
19 words
A field programmable gate array as recited in claim 27, wherein the combinatorial logic circuit is a look-up table.
Claim 33
Dependent Claim
45 words
A field programmable gate array as recited in claim 25, wherein the first output driver further comprises an output, and wherein the second output driver further comprises an output, the outputs from the first and second output drivers providing outputs from the programmable function unit.
References Cited (Backward Citations)
US4706216A
Cited
US4758746A
Cited
US5155389A
Cited
US4786904A
Cited
US5231588A
Cited
US5122685A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |